Choose a signal or power integrity learning path

Both disciplines, in eight steps

You know basic electronics — Ohm’s law, capacitors, a bit of AC theory — and you have just been handed a high-speed board.

This path deliberately crosses from signal integrity into power integrity and back, because the two are one problem and the place they meet is where real designs fail. Each step names what it assumes, the one thing it will change your mind about, a five-minute experiment, and a question you can only answer by applying the idea somewhere it was not demonstrated. Experienced engineers should skip straight to the lab or the diagnosis at step 8.

1. Units, edges, and time of flight A picosecond is a distance. Everything after this depends on being able to convert between the two without thinking.

   assumes

   nothing

   you will be able to

   turn a rise time into a bandwidth and a length into a delay, and say which rise-time convention you used

   corrects

   that there is a single factor between 20–80% and 10–90% rise times. There is not: it is 0.631 for an exponential edge, 0.750 for a ramp

   five minutes

   take the fastest edge on your current design and compute the length at which it stops being a wire

   transfer check

   a datasheet quotes 45 ps 20–80%. What is the knee frequency, and what did you have to assume to get it?

2. Source, line, load: launch and reflection A wave leaves the driver before information from the load can return. The returning wave and its timing explain the observed response.

   assumes

   step 1

   you will be able to

   predict the launched voltage from the source divider, and the settled voltage from the terminations, before running anything

   corrects

   that a matched load absorbs half the power. It absorbs all of the incident wave — the half is a property of the source divider, and they are different facts

   five minutes

   Lab A: set the far end open, then short, and predict the far-end voltage and current separately before you look

   transfer check

   the source is 50 Ω and the far end is open. Why does the ringing stop after one round trip rather than continuing?

3. Return current and reference continuity The other half of every circuit, and the half that is not on the schematic.

   assumes

   step 2

   you will be able to

   look at a layer transition and say where the return current goes and what it costs

   corrects

   that return current takes the shortest path. Above a few megahertz it takes the lowest-inductance path, which is directly under the signal

   five minutes

   find a net on your board that changes reference plane, and locate the nearest return via

   transfer check

   a trace crosses a gap in its reference plane. The signal is 100 MHz and clean; at 2 GHz it is not. What changed, given the gap did not?

4. Channel memory and sampling A channel remembers. The bit you are trying to read is competing with the ones before it.

   assumes

   steps 1–3

   you will be able to

   read a pulse response, name the cursor and the post-cursors, and connect a closed eye to a specific earlier bit

   corrects

   that a loss number predicts an eye. Lab B's stub preset has the same 14 dB and the same rate as the baseline and a fifth the opening

   five minutes

   Lab B: press rate only. The board is bit-identical — the S-parameters do not move at any frequency. Predict what closes the eye before reading the answer

   transfer check

   two channels have identical insertion loss at Nyquist. One has a notch at 7 GHz. Which eye is worse, and which panel would show you that?

5. Load current to voltage excursion Here the subject changes. A processor's current step has to come from somewhere, and the rail moves while it arrives.

   assumes

   step 1. Nothing from 2–4 — this is the other discipline, starting again

   you will be able to

   turn a current step and an impedance into a voltage droop, and say which part of the network supplied it

   corrects

   that a power rail is a node. It is a network with a different impedance at every frequency and every position

   five minutes

   Target impedance: compute the impedance your own rail needs from its current step and its tolerance

   transfer check

   the rail meets its target impedance at every frequency you swept, and still droops too far. What did the sweep not cover?

6. Decoupling, and why more capacitance can fail The one result in power integrity that is genuinely counter-intuitive, and it is measurable.

   assumes

   step 5

   you will be able to

   look at two capacitor banks and predict where they will fight, and know which knob damps it

   corrects

   that adding decoupling always helps. In Lab C, quadrupling the board capacitors raises the mid-band peak from 57 to 61 mΩ, because parts in parallel divide the ESR that was damping it

   five minutes

   Lab C: predict the direction before you change the capacitor count, then use the result to refine your reasoning

   transfer check

   you need to lower a 60 mΩ peak at 7 MHz. You may add parts, change their ESR, or move them. Which helps, and why do the other two not?

7. Where the two disciplines meet Supply noise moves a receiver's sampling instant. This is the case that cannot be assigned to either discipline, and it is where real escapes live.

   assumes

   steps 4 and 6 — you need both halves for this one

   you will be able to

   explain how a PDN resonance becomes a timing failure, and say which of three injection points a given noise frequency reaches

   corrects

   that supply noise and timing are separate budgets. The same millivolts of ripple cost you nothing or everything depending on where in the clock path they enter, and on the loop bandwidth

   five minutes

   set the ripple to 1 MHz at the VCO, then at the reference. Same amplitude, and the loop corrects one and follows the other

   transfer check

   an eye closes only when a nearby core is busy. The channel is unchanged. Name two mechanisms that could do this and one measurement that separates them

8. An unseen diagnosis Apply the ideas above to a diagnosis whose cause has not been given in advance.

   assumes

   steps 1–7

   you will be able to

   choose which domain to look in first, and say what each measurement would rule out

   corrects

   that debugging is about finding the problem. It is about eliminating explanations, which is why the order of measurements matters more than their precision

   five minutes

   Lab B: press hide a discontinuity, read its position off the TDR panel, and commit to a number before checking

   transfer check

   a link fails at 32 GT/s and passes at 16. Write down three candidate causes and the single cheapest measurement that separates them

What this path does not give you. Compliance numbers, a sign-off procedure, or a substitute for a field solver and a measurement. Every model here says what it computes and what it is known not to do — the verify tab on any panel, and the model contracts for all of them at once.

Practising signal integrity

You work in signal integrity and want to examine conventions, assumptions, and subtle failure mechanisms.

Weighted towards the things that cause disagreements: conventions, what models assume, and where equalisation stops helping.

1. Time-Domain and Frequency-Domain Analysis what each transform assumes, and where it breaks
2. S-Parameters: Insertion Loss, Return Loss, and Mixed Mode passivity, reciprocity and causality as three separate claims
3. ISI why a DFE can be exact and a CTLE cannot
4. What closes the eye four impairments, four signatures, four different fixes
5. Lab B: Channel Response, ISI, and Eye Diagrams click a post-cursor and see the bit that caused it
6. Equalisation which cursor each block can reach, and why
7. Receiver Sampling, Clock Recovery, and Jitter Tolerance where the margin is created on a modern link
8. Vias the impairment no equaliser can undo
9. Statistical vs time-domain two methods, opposite blind spots
10. Reporting margin why two correct analyses differ by a factor of two

Practising power integrity

You own a rail, and you want the parts that are counter-intuitive.

Built around the results that surprise people: adding capacitance making things worse, and fixes that cannot reach the problem.

1. What is the PDN? a chain of sources, each useless above its own band
2. Three droops, three owners read the dip’s width, not its depth
3. Anti-resonance parallel LC is a maximum — every peak is this
4. Real capacitors the marked value is not the value you get
5. Lab C — regulator to die which bank supplies the current, in amps, at every frequency
6. Target impedance a useful line, and what the single number hides
7. Simultaneous Switching Noise and Ground Bounce v = L·di/dt across a shared return
8. PDN-induced jitter where a power problem becomes a timing problem
9. Package Interconnects as Transmission Lines transfer impedance, and the limits of lumped

Debugging something right now

You have hardware, a symptom, and not much time.

Read the first one, then jump to whichever symptom matches. Every page in this route ends with a fault-finding list keyed to what you are seeing rather than to what is causing it.

1. Debug playbook start here — how to pick a measurement that actually discriminates
2. Measuring it before you trust the instrument, check what it added
3. What closes the eye a closed or noisy eye: which of four impairments
4. Jitter taxonomy jitter: bounded or unbounded, and what that implies
5. Three droops a rail moving: measure how long, not how big
6. Crosstalk noise that appears only when neighbours are active
7. Return current paths coupling between nets that never run near each other
8. Lab D — ADC interference a measured value that is noisy or offset, with something switching nearby
9. Correlation when simulation and measurement disagree, what that can mean