SI in practice / 04
Statistical and Time-Domain Channel Simulation
There are two ways to predict a link's error rate, and they fail at opposite things. One computes the probability distribution directly and reaches 10−18 as cheaply as 10−6, but only works if the link is linear and time-invariant. The other simulates actual bits and handles anything, but cannot run long enough to see a rare event.
When qualifying a high-speed serial link, the single overarching question is always: will this channel achieve its Bit Error Rate (BER) target with positive voltage and timing margin? For modern enterprise standards, that target is typically an uncorrected BER of 10-12 for NRZ or 10-4 pre-FEC for PAM4. But verifying a BER of 10-12 via brute-force transient simulation means driving, sampling, and checking at least 1012 individual bits. At 32 Gbps, simulating one trillion bits on SPICE or a standard transient solver would take months of compute time for a single trace.
To escape this computational barrier, signal integrity methodology divides into two competing philosophies: time-domain (bit-by-bit) simulation and statistical analysis. Time-domain simulation clocks bits sequentially through the driver, channel, and receiver, faithfully capturing non-linear driver saturation, dynamic adaptation loops, and DFE error propagation — but it is practically constrained to a few million bits (106, sampling down to 10-5).
Statistical simulation (the mathematical foundation of IBIS-AMI statistical mode and standards-compliance tools like Channel Operating Margin, COM) inverts the problem. By assuming the channel is Linear Time-Invariant (LTI), it captures the channel's single-bit response once, and then uses probability theory and discrete convolutions to calculate the exact probability distribution of ISI and noise across all possible bit sequences. It reaches 10-12 or 10-18 in seconds. Mastering when statistical assumptions are valid — and where they fall off a cliff — is central to trusting link simulation margins.
Two ways to answer the same question
The question is: at a given sampling point, what is the probability that the voltage is on the wrong side of the threshold? A bit error rate is exactly that probability.
You could measure it. Drive real bits through the channel, sample them, count the mistakes. This is time-domain simulation, and it has one enormous virtue: whatever is in the model actually happens. Non-linear drivers, DFE error propagation, CDR dynamics — all of it, for free, because you are not modelling the behaviour, you are running it.
Or you could compute it. If you know the channel's pulse response, you know how much each neighbouring bit contributes to the sample. Enumerate the possibilities, combine their probability distributions, and you have the distribution of the sampled voltage without ever sending a bit. This is statistical simulation, and its virtue is that a distribution has tails — so 10−18 costs no more than 10−6.
Neither is better. They are good at different things, and knowing which one you are holding is most of using them well.
Two methods, two blind spots
Statistical simulation starts from the channel's impulse response, decomposes it into cursor and ISI contributions, and convolves their probability distributions to build the complete voltage distribution at the sampling instant. Because it computes a distribution rather than sampling one, it reaches arbitrarily low probabilities immediately — 10−12 and 10−18 cost the same.
Time-domain simulation drives real bits through the channel and looks at what comes out. Whatever is in the model happens: non-linear drivers, DFE error propagation, CDR dynamics, burst-mode turn-on. The limit is arithmetic — a million bits samples 10−6, and no run length available in practice reaches 10−12.
When each one lies to you
Statistical lies when the channel is not LTI. Its whole method rests on superposition, so anything that violates it is either approximated or silently absent:
- DFE error propagation — a decision error feeding back is fundamentally non-linear.
- Non-linear or level-dependent drivers, which matters more for PAM4 than NRZ.
- CDR dynamics and jitter tracking, usually handled by a separate analytical model rather than simulated.
- Anything that changes with time: adaptive equaliser convergence, burst-mode acquisition, thermal drift.
Time-domain lies by extrapolation. Its raw result is honest but stops six decades short, so the reported number comes from fitting Gaussian tails to what was observed — which inherits every assumption in that fit, and is optimistic exactly when a jitter component has been mis-classified as random.
One practical note: both methods are only as good as the S-parameters underneath them. A non-causal or non-passive file produces confident, well-formatted results in either flow, and neither will warn you.
Why this decides how your board behaves
- Only one of them can answer a compliance question directly. A specification written at 10−12 is beyond any practical time-domain run, so either you compute the distribution or you extrapolate a measured one. Both are models.
- Only one of them can see error propagation. A DFE making a wrong decision and corrupting the next few bits is a sequential, non-linear event. A statistical method built on superposition has no term for it.
- They disagree in ways that are informative. When they do, the difference is usually a violation of linearity or time-invariance — which is a finding about the link, not about the tools.
- Both inherit their channel model. Neither can rescue a non-causal Touchstone file or a channel measured over the wrong bandwidth.
What to do about it
Use statistical for margin, time-domain for behaviour. That is the division that works: statistical answers "how much margin at what BER", time-domain answers "what does this receiver actually do".
Run both when the answer matters. Agreement is meaningful evidence. Disagreement tells you where the link is not behaving linearly, which is exactly what you want to know before signing anything.
Check that the statistical run's assumptions hold. Adaptive equalisation, a CDR that moves the sampling point, burst-mode turn-on and any transmitter non-linearity all break the assumptions quietly rather than loudly.
Say which one produced any number you report. A margin from a statistical run and a margin from a time-domain run are different quantities with the same units, and quoting them interchangeably is a common and expensive confusion.
- Statistical much more optimistic than time-domain. Something is non-linear or time-varying. Prime suspects: DFE error propagation, an adapting equaliser, or a driver that is not linear at the swing you are driving.
- Time-domain more optimistic than statistical. Usually the run is too short to have hit the worst pattern. Check the pattern length against the channel's memory.
- Either one disagreeing with hardware in the tails only. Suspect a random contributor neither model has — most often supply noise, which channel simulators exclude unless asked.
- A statistical result that changes a lot with the pattern you specify. It should not, if the method is genuinely enumerating. That sensitivity means it is approximating somewhere.
Go deeper — what superposition buys, and where statistical models break down
The statistical method works because a linear time-invariant channel obeys superposition: the response to a bit stream is the sum of the responses to each bit individually. So the sampled voltage is
That last step is the whole trick. Convolving distributions gives you the complete distribution of y, tails included, in one calculation — and the tails are precisely what a sampled run cannot reach. You are not estimating a rare event; you are computing its probability.
Where the statistical model breaks down. Everything in that analytical expression hinges on the channel and transceivers behaving as an ideal Linear Time-Invariant (LTI) system with independent, stationary noise. In high-speed hardware, four dominant mechanisms violate this premise:
- Non-linear equalization (DFE): A decision feedback equaliser is fundamentally state-dependent — it slices an analog level to make a hard digital decision, then feeds it back. Statistical engines evaluate an "ideal" DFE by subtracting post-cursor tails under the assumption that past decisions are always 100% correct. But in the extreme tails (the exact region deciding a 10-12 BER), an erroneous decision inverts the feedback sign and triggers a burst error event. Statistical convolution cannot model this error propagation; it predicts an artificially clean tail.
- Silicon non-linearities: Real CMOS output stages suffer from non-linear driver impedance, voltage-dependent junction capacitance (Cj(V)), and rail compression. Superposition assumes that doubling the input stimulus doubles the output voltage; in a saturated driver, transitions round off non-linearly.
- Dynamic adaptation loops: In live silicon, CTLE peaking gain and DFE tap coefficients adapt continuously using Least Mean Squares (LMS) algorithms. The channel transfer function is therefore time-varying, not static. Statistical models must evaluate a single frozen set of tap weights, obscuring whether the real receiver would converge or wander.
- Correlated and non-stationary jitter: Statistical engines convolve uncorrelated Gaussian distributions. They cannot capture Power Supply Induced Jitter (PSIJ) modulated by transient core current, nor can they capture data-dependent jitter (DDJ) where specific multi-byte patterns consistently trigger extreme edge shifts.
When time-domain simulation is unavoidable. While statistical simulation is unmatched for rapid design-space exploration, sensitivity sweeps, and multi-corner sign-off, time-domain (bit-by-bit) simulation is mandatory for specific engineering sign-off gates:
- Clock and Data Recovery (CDR) lock validation: Verifying phase-lock acquisition time, tracking bandwidth, frequency offset tolerance, and resistance to cycle-slipping during long run-length sequences.
- Adaptive convergence verification: Ensuring that auto-negotiation and link training converge reliably to the optimal equalization settings without settling in local sub-optimal minima.
- Pathological pattern stress: Driving worst-case compliant test patterns (like CJTPAT, CRPAT, or PRBS31 stress bursts) to evaluate burst error susceptibility and verify that the forward error correction (FEC) architecture can absorb the resulting error distribution.
A last point about what "reaching 10−18" means. The statistical method computes that number exactly under its assumptions — but the assumptions were never verified at 10−18, and could not be. The precision is real; the accuracy is inherited from a model validated several decades higher up. That is worth remembering before quoting a number with that many zeros.
In the real world
The two methods map onto two moments in a project. Statistical belongs early, when you are exploring a design space and want margin numbers for many variants quickly. Time-domain belongs later, when a specific receiver with specific settings has to be shown to work.
The failure to avoid is using one for the other's job — sweeping a hundred stackup variants in the time domain, or signing off a DFE-heavy link on a statistical margin alone. Both happen, and both waste the strength of the tool being used.