Package & board / 07
Package Interconnects as Transmission Lines
A package is drawn as a set of connections and behaves as a network of coupled inductances. The point at which that distinction starts to matter — where a lumped model stops describing what the hardware does — is where most late-surfacing problems live, because it is also where one organisation's model ends and another's begins.
In traditional circuit board design, engineers often treat an IC package as a transparent electrical conduit: signals enter through a BGA solder ball and are assumed to arrive instantaneously at the silicon die. For low-speed microcontroller buses with microsecond rise times, this simplification is harmless — a 10 mm package trace is so short relative to the electrical wavelength that it behaves as a simple lumped node with a fraction of an ohm of resistance.
Modern high-speed SerDes and memory interfaces, however, operate on sub-50-picosecond edge rates. In a package dielectric, electromagnetic signals propagate at approximately 6 inches per nanosecond (about 150 μm/ps). For a 25 ps rise time, the spatial extent of the rising edge is under 4 mm. The moment a signal's physical rise length becomes comparable to or shorter than the package trace length, the lumped-element wire assumption evaporates completely.
A 10 mm trace inside a package substrate is not a wire; it is a full distributed transmission line subject to impedance mismatches, high-frequency attenuation, and standing wave reflections. Worse, this electromagnetic boundary coincides exactly with an organizational fissure: the package substrate is designed by the semiconductor packaging group, while the printed circuit board is designed by the system hardware team. Critical signal and power integrity failures cluster disproportionately at this interface, where model handoffs, unaligned reference planes, and mutual coupling fall between engineering silos.
Two boundaries in the same place
A package sits at two boundaries at once, and they coincide unhelpfully.
The electrical boundary is where a lumped description stops working: where the connections are long enough, or coupled enough, that calling them "an inductance" hides what matters.
The organisational boundary is where the board team's model ends and the package team's begins — and, one level further in, the silicon team's.
Problems cluster where these two coincide, which they do by construction. Every significant PDN resonance sits at a handoff, and every handoff is somebody else's model.
Mutual inductance: the term that is usually dropped
Self-inductance is the familiar term: a current changing in a loop develops a voltage across that loop. Mutual inductance is the same effect between two loops — a current changing in one develops a voltage in the other.
In a package, adjacent signal returns are close together and therefore coupled. So the usual first-order picture of SSN — N drivers sharing one self-inductance — understates it, because each driver also induces voltage in its neighbours' loops directly.
This is also why pin assignment is an electrical decision. Distributing power and ground among the signals rather than clustering them reduces both the shared self-inductance and the mutual coupling, and it is nearly free at the moment it is decided.
Return via placement, quantified
When a signal changes reference plane, its return has to change too. The cost of not providing a path is an inductance, and it is worth turning that from a judgement into arithmetic.
A useful field estimate is about 1 nH per millimetre of extra return loop. Compare its reactance at your knee frequency against the line impedance:
"There is no return via here" sounds like a style comment until it is stated in ohms. See layer transitions.
Transfer impedance: the question one port cannot answer
A driving-point impedance answers "how much does the rail move when this block draws current?" It says nothing about "how much does a noisy block over there disturb me?"
That second question is a transfer impedance, and it is how two circuits with no shared net end up coupled — through a shared plane, a shared package layer, or a cavity resonance. It has two consequences worth carrying:
- A rail can meet its own target impedance everywhere and still be disturbed by a neighbour.
- Fixing a peak seen at one port can move it to another, because the currents circulating in a resonance are local.
Where the lumped abstraction stops
Calling something "an inductance" is an abstraction with a validity range — and it is worth being precise about which abstraction expires, because two different ones get confused here. A single lumped value is a much weaker claim than lumped modelling, and most of what people call "the lumped model breaking down" is the first one failing while the second is still perfectly serviceable.
- Coupling to neighbours does not break lumped modelling. A two-terminal inductor has no awareness of what is beside it, but a coupled inductor pair does: mutual inductance is an ordinary lumped element, written as an off-diagonal term in an inductance matrix, and every circuit simulator handles it. What fails is the uncoupled approximation. That is a modelling choice you made, not a limit of the method — and the fix is to extract the matrix rather than to abandon circuits.
- Nor does a position-dependent voltage. "A plane is not a node" is true, and the answer is more nodes: a plane meshed into a grid of lumped inductances and capacitances reproduces its impedance and its cavity modes, which is how most commercial PDN tools work. What fails is the single-node approximation. This site's own PDN lab is a five-node ladder for exactly that reason, and each node has a different impedance.
- What genuinely sets the boundary is the discretisation against the electrical size. A lumped element assumes the voltage across it and the current through it are one number each, which requires it to be small compared with a wavelength at the highest frequency you care about. So the real question is not "is there coupling" or "does position matter" but: is my mesh fine enough for the bandwidth and the error I need? A tenth of a wavelength per cell is the usual working figure. Below that bandwidth a lumped mesh is not an approximation to a field solution — it converges to one.
- Frequency dependence is a separate axis. Skin effect makes resistance rise as √f, so a single R is a value at one frequency. That is fixed by making the element frequency-dependent, not by leaving the lumped world — which is exactly what the causal line model on the channel lab does.
- And what actually cannot be lumped is radiation, and propagation you need to resolve rather than approximate: a structure carrying a travelling wave whose phase across it matters, an antenna, a cavity above its first mode where you want the field pattern and not just the terminal impedance. At that point you want a field solver because you are asking a field question.
The practical consequence is that "the lumped model has expired" is almost never the right diagnosis on its own. Ask which simplification expired — uncoupled, single-node, single-frequency, or too coarse — because three of those four are fixed inside the circuit description, and only the fourth sends you to a field solver.
This site's own PDN lab is explicitly lumped, and its model contract says so: no cavity modes, no spatial distribution, everything in a bank at the same place. That is a useful model with a stated edge, which is the only honest way to use an abstraction.
What to do about it
Get a package model early, even a crude one. A single lumped inductance and capacitance is far better than an ideal source, because it at least puts a resonance near the right frequency. Precision can come later; the existence of the peak cannot be added later.
Write down the partition. Where does each model end, where does the next begin, are the ports at the same physical plane with the same reference? Most co-analysis failures are bookkeeping failures.
Treat a result's sensitivity to the boundary condition as the finding. If changing the termination changes the answer a lot, the boundary is electrically active and needs a real model — not a better guess.
Ask for transfer impedance, not just self impedance, on any rail shared between a noisy block and a sensitive one.
- SSN worse than L·di/dt predicts. Mutual inductance between adjacent returns. A first-order model will always understate it.
- Simulation and measurement agree below ~100 MHz and diverge above. Classic truncation signature: the board dominates below, the package and die above.
- A measured peak the simulation does not have. Check whether the model stops at the boundary where that peak lives, then compare against 1/(2π√LC) for the package inductance and die capacitance.
- Noise at one block caused by another with no shared net. Transfer impedance. A single-port analysis cannot show it.
- A model that behaves differently depending on where you probe it. The lumped abstraction has expired — you need a distributed model.
Go deeper — partition coupling, and why crude-but-early beats exact-but-late
Splitting a structure is only valid where the fields are quiet. Two vias solved independently and cascaded is not the same as two vias solved together, and the difference is exactly the coupling you cut through. So a partition boundary should be placed somewhere the fields have decayed — several dielectric heights from anything interesting — rather than wherever the organisational boundary happens to fall.
Those two criteria rarely coincide, which is the deep reason co-analysis is hard. The electrically correct place to cut is not the place the contracts cut.
Why crude-and-early wins. The value of an analysis is entirely in what it lets you change. A package inductance target, an on-die capacitance budget and a bump map are all decided early, and a rough co-analysis at that moment informs all three. An exact one after tape-out can only confirm or alarm.
So the practical sequence is staged: start with crude terminations and refine them. The first version answers "is there a peak near here?"; only the last answers "how tall is it?". Doing it in that order means the structural decisions are informed at the point they can still be made.
And one boundary people forget entirely. Signal and power share the same physical structures — a driver's return current flows through the same package and board network the PDN analysis covers. So the boundary between an SI model and a PI model is itself a partition with all the same problems, and it is usually drawn without anyone noticing they drew it.
In the real world
The package is the part of the chain most likely to be missing when the first serious simulation runs, and its absence hides exactly the resonances that matter. That is a scheduling problem as much as a technical one — the models come from three organisations with different timelines and different confidentiality constraints.
Which makes the useful move a procurement one: ask for the models at the start, accept rough ones, and say clearly what decision each version is meant to inform. A crude model at the right moment beats an exact one after the decision has been made.
Related
- Package families — where the inductance comes from
- PCB Layer Transitions and Return-Path Stitching — the return via, in detail
- Chip-Package-System Power Integrity Co-Analysis — the partition problem
- Simultaneous Switching Noise and Ground Bounce — what mutual inductance does
- Plane resonance — where lumped stops working