Power Integrity / 05
PDN Frequency Regions: Board, Package, and Die
Apply a load step and the rail does not sag once. It sags three times, on three very different timescales, because three different stores of charge run out one after another before the next takes over. Knowing which droop you are looking at tells you which hardware can possibly fix it — and, more usefully, which cannot.
Why one step produces three dips
When you capture a high-speed load transient on an oscilloscope, you do not see a single, smooth voltage sag. Instead, you see a jagged sequence of three distinct dips unfolding across vastly different timescales: one in the first nanosecond, another tens of nanoseconds later, and a third stretching across microseconds. To an untrained eye, this looks like random ringing or chaotic noise. But it is actually an orderly organizational chart of the system's power architecture.
Power integrity is fundamentally a division of labor: a strict jurisdictional map where the VRM, board capacitors, package planes, and on-die capacitors each “own” a specific frequency band. Because each tier is separated from the transistors by a different amount of physical distance and loop inductance, each tier runs out of stored charge before the next slower, larger tier can respond. Knowing which hardware tier governs each timescale is the most critical diagnostic rule in PI: an engineer who tries to solve a 1 ns droop with a board capacitor will spend weeks achieving nothing, because that event sits entirely outside the board's jurisdiction.
Picture the instant a load step arrives. The current has to come from somewhere, and the candidates are at different distances — on-die capacitance a few micrometres away, package capacitance a millimetre away, board capacitors centimetres away, the regulator further still.
Between each of those and the load is some inductance, and inductance sets how quickly that source can start delivering. So the nearest store responds first, because it has the least inductance in the way. It is also the smallest, so it runs down quickest — and the rail sags until the next store, further away and slower, picks up.
That handover is a droop. There are three of them because there are three handovers, and each one happens on the timescale set by the inductance between those two stores. The pattern is a relay race where each runner is faster than the next but carries less.
Three droops, three owners
What does generalise is the reasoning: charge for a fast transient must come from somewhere electrically close, and series inductance decides how close that has to be. Use the table as a way to ask which store is supplying your event, not as a set of fixed frequencies.
Apply a load step and watch the rail. It does not sag once; it sags three times, on three timescales, and each dip is a different part of the network running out of stored charge before the next one takes over.
| Droop | Timescale | Frequency | Held up by | Fixed by |
|---|---|---|---|---|
| First | ~1 ns | hundreds of MHz | on-die capacitance | die and package only |
| Second | ~10–100 ns | tens of MHz | package caps, board ceramics | package, board mounting |
| Third | ~1–10 µs | ~100 kHz | bulk caps, then the VRM | bulk capacitance, VRM loop |
Identify which droop you are looking at and the list of things worth trying collapses to a handful. Skip that step and you can spend weeks adding capacitors on the wrong side of a fence.
The fence is inductance
Every stage is separated from the next by series inductance — balls, vias, bond wires or bumps, plane spreading. That inductance rises with frequency as an impedance, and above some frequency it is simply larger than anything the far side can offer. Charge on the board side physically cannot get to the die fast enough, and the die is on its own.
The converse is just as useful and much cheaper to act on. If the problem is a third droop — microseconds, a workload transition, a big power-state change — then on-die capacitance is irrelevant to it and the die team has nothing to contribute. It is bulk capacitance and VRM response, and it is a board and regulator conversation.
Where this gets genuinely hard is that the handoffs between stages are exactly where the impedance peaks are, so a problem can sit in two owners' territory at once. That is the case chip-package-system co-analysis exists for: neither side's model, simulated alone, contains the resonance.
Why this decides how your board behaves
- It tells you what cannot possibly help. This is the highest-value fact in the subject. A first-droop problem cannot be fixed from the board, at any cost, because the package inductance isolates the board from the die on that timescale. Knowing this saves weeks.
- Each droop has a different owner. The first belongs to silicon and package design; the second to package and board together; the third to the regulator and bulk capacitors. Those are usually three different teams.
- The worst one is not always the deepest. A shallow droop that coincides with a sensitive block's operation can matter more than a deeper one that does not.
- Load release is its own event. The rail overshoots when the current stops, because the inductance is still pushing. Droop sets timing margin; overshoot sets the high-rail limit, and they are checked separately.
What to do about it
Measure the timescale first, always. Everything else follows from it. A nanosecond dip and a microsecond dip look similar on a badly scaled plot and have nothing in common as problems.
For the first droop, the only levers are on-die and in-package. More on-die decoupling capacitance, lower package inductance, or reducing the di/dt itself — staggering clock-gate release so the step is spread over more cycles is often the cheapest fix available and costs no hardware at all.
For the second, attack mounting inductance. This is the band where board ceramics and package capacitance hand over, so the loop inductance of both is what sets it.
For the third, look at the regulator's loop. Its bandwidth decides where it stops being able to help, and bulk capacitance covers the gap between that and the ceramics. See VRM loop bandwidth.
- Read the dip's width, not its depth, to identify it. Width names the owner; depth only tells you how bad it is.
- A droop that did not change when you added board capacitors. It was the first droop. Stop adding parts.
- Ringing on the recovery rather than a clean settle. There is an anti-resonance between the two stages handing over. Its frequency identifies which two.
- Failures that only happen on a workload transition. Look at power-state exits and clock-gate releases — the largest di/dt on a modern SoC is almost never the steady workload.
Go deeper — what sets each timescale, and why this decomposition is a convenience
Each handover happens at roughly the resonant frequency of the inductance between two stores and the capacitance of the nearer one:
That is the same expression as the anti-resonance frequency, and deliberately so: a droop in time and a peak in frequency are the same event seen two ways. If you have an impedance curve and a transient plot of the same PDN, each droop corresponds to a peak, and their frequencies match. Checking that they do is a good way to validate a model.
The decomposition is a convenience, not a law. The three bands describe a common architecture — a board regulator, a package with its own capacitance, a die with on-die decoupling — and the numbers move with every one of those choices. A design with no package capacitance merges two of them. One with an integrated voltage regulator loses the longest. A distributed plane contributes a spread of overlapping resonances rather than a single clean peak, and peaks can appear within a stage rather than only at the boundaries between them.
What does generalise is the reasoning: charge for a fast transient must come from somewhere electrically close, and series inductance decides how close that has to be. Use the bands as a way to ask which store is supplying your event, not as a set of fixed frequencies.
One practical consequence of the time-frequency equivalence: a transient measurement is often easier than an impedance measurement and tells you much of the same thing. A step response with a clean scope shot gives you the droop timescales directly, and from those you can infer where the peaks are without ever connecting a VNA.
In the real world
The three-droop picture is the most useful diagnostic frame in power integrity, and its value is almost entirely in ruling things out. Most PI debugging time is lost to fixing the wrong band — adding board capacitance to a package problem, or re-tuning a regulator for a nanosecond event.
So the first question on any rail problem is not “how big is it?” but “how long is it?” One measurement, and two thirds of the possible fixes are eliminated before you have opened the layout tool.