Real Capacitors: Bias, Tolerance, Temperature, and Mounting

By Geetansh Arora — Principal SI/PI Engineer15 Sep 202610 min

The capacitance printed on a decoupling capacitor is not the capacitance you get. DC bias can remove half of it, temperature moves it, ageing moves it again, and the mounting geometry decides how much of what is left can actually reach the load. A PDN simulated from datasheet values is therefore answering a question about a different circuit — and not always a flattering one. Less capacitance raises the floor where that bank was supposed to work, which is worse; but it also moves the resonance against its neighbour, and a higher ESR damps it, which at that frequency is better. Which way any given peak moves is a property of the network, not a rule you can apply in advance.

One part, one mount · 1 kHz – 100 MHz analytical marked — delivered — SRF —

Impedance magnitude vs frequency — log/log. The shaded region is everything consistent with what you know.

as marked at your operating point consistent with what you know

Part—

Marking, case and rating only — no vendor curve is reproduced here

Capacitance retained55% retained

You supply this. Get it from your vendor’s curve, for your part, at your bias

How well you know it± 15 points

Lot spread, vendor spread, and the slow settling after bias is applied

Part ESL600 pH

Declared, not derived — your vendor publishes it

Return via spacing1.00 mm

1.6 mm board, 0.3 mm barrels — loop computed exactly, not estimated

Custom

Ltot — |Z| at SRF — resonance moves —

What a marking actually promises

In schematic entry tools and component bills of materials, a capacitor is defined by an idealized, static value: a 22 µF 0603 ceramic capacitor is assumed to deliver exactly 22 microfarads of pure capacitance. If a PDN calculation demands 100 µF of charge storage to satisfy a target impedance, it is tempting to simply place five of those 22 µF capacitors in parallel and assume the requirement is met.

In physical reality, the capacitor on your BOM is virtually never the capacitor operating on your circuit board. High-density multilayer ceramic capacitors (MLCCs) rely on ferroelectric barium titanate dielectrics (such as X5R and X7R) to achieve enormous capacitance in tiny packages. But that high permittivity comes with a steep physical penalty: when exposed to an electric field from a DC working voltage, the crystal domains saturate, and effective capacitance plummets by 40% to 70% or more. Add manufacturing tolerances, thermal shifts across operating corners, decades of aging, and the parasitic loop inductance of surface vias, and that nominal 22 µF part may deliver less than 6 µF of real capacitance behind an ESL three times higher than the vendor's component datasheet.

A 100 nF 0402 capacitor is characterised at a specific voltage, temperature and signal level — usually near zero bias, 25 °C and a small AC excitation. Your rail is none of those.

Class II ceramic dielectrics, which is what X7R and X5R are, get their high capacitance density from a ferroelectric material whose permittivity depends on the field across it. Apply a DC bias and the permittivity falls, and with it the capacitance. That is not a defect; it is how the material works.

The four things that move the value

DC bias. The largest effect, and the one most often missed. A small-case-size part at its rated voltage can lose most of its capacitance, and the effect is worse for smaller packages at the same value — because the dielectric is thinner, so the field is higher.
Temperature. X7R holds ±15% over −55 to +125 °C; X5R holds the same band over a narrower range. That tolerance is on top of the bias effect, not instead of it.
Initial tolerance. ±10% or ±20% is typical, and it is the smallest of these four.
Ageing. Class II dielectrics lose capacitance logarithmically with time from their last thermal reset — a few percent per decade of hours. Soldering resets it, so the clock starts at assembly.

The practical consequence Stack a realistic bias derating on top of tolerance, temperature and ageing, and a part marked 100 nF may be delivering half that in service. Simulate the PDN with the marked value and the impedance curve you get is not the one the board has. It is tempting to add that the error always flatters the design. It does not, and the next section is about why that matters more than if it did.

Derating does not simply make things worse

Take the 22 µF part in the panel above, mounted with a 1 mm return via, and derate it to 35% of its marking — the kind of loss a high-density Class II part can show at a real rail voltage. Its delivered capacitance falls to 7.70 µF, and because the self-resonant frequency goes as one over the square root of capacitance, its resonance climbs from 800 kHz to 1.352 MHz. Now compare the impedance the board actually has against the impedance a simulation using the marking predicts:

|Z| of one mounted 22 µF part: marked value against 35% retained
Frequency	Marked	Derated	Ratio
10 kHz	723.63 mΩ	2066.94 mΩ	2.856×	worse, by exactly the capacitance you lost
751 kHz	3.56 mΩ	19.33 mΩ	5.436×	worst point — the marked model resonates here and the part does not
1.111 MHz	6.81 mΩ	6.81 mΩ	1.000×	crossover
1.380 MHz	10.79 mΩ	3.11 mΩ	0.288×	best point — now the part resonates and the model does not
20 MHz	225.80 mΩ	225.13 mΩ	0.997×	both inductive; the capacitance has stopped mattering

Three things in that table are worth more than the headline. Well below resonance the ratio approaches exactly one over the retained fraction — 1/0.35 = 2.857, against 2.856 measured at 10 kHz — because there the part is nothing but its capacitance, so losing 65% of it costs you 65% of it and not a decibel more. Around the marked resonance the error is 5.44×, and it is large precisely because the marked model predicts a deep null that the real part does not have. And a little higher up the error reverses: at 1.380 MHz the real part is 3.47× better than the marked model says, because now it is the real part that is resonating.

So the marked-value simulation is not conservative and it is not optimistic. It is wrong in one direction in one band and wrong in the other direction in the next, with a crossover at 1.111 MHz that lands wherever the derating happens to put it. That is the reason a derating you cannot bound is worse than a derating that is merely large: a large known loss can be designed around, and an unknown one moves the sign of your error across the band.

Why the panel will not tell you your derating It has no honest way to. Novak and colleagues at DesignCon East 2011 measured MLCCs from six vendors and found that the bias dependence of the same nominal part differs markedly between them, that X7R is not reliably better than X5R — sometimes not even within one vendor — and that beyond the immediate change there is a slow settling worth as much as another 25% over a few minutes. Ten samples of a single order code spread visibly. A panel that shipped one curve and called it “22 µF X5R” would be teaching you that derating is something you look up. It is something you bound, from your vendor’s curve, for the part you are actually buying, at the bias you are actually applying. The panel takes that number from you and shows you what the uncertainty in it costs.

ESR is not a constant either

Datasheets often quote a single ESR, and it is a value at one frequency. Real ESR has two mechanisms that move in opposite directions:

Dielectric loss dominates at low frequency and falls as frequency rises.
Metal loss in the electrodes and terminations rises with frequency, because of the skin effect.

The result is a shallow minimum, usually somewhere near the part's self-resonant frequency. That matters because ESR is the damping in every anti-resonance — so a model using a single flat ESR gets the peak heights wrong, and gets them wrong differently in different bands.

Mounting: the inductance you built

The part's own ESL for an 0402 is a few hundred picohenries. The loop it sits in — pad, via down to the plane pair, along the planes, and back — is routinely two to three times that. So the mounting dominates, and it is geometry rather than a purchasing decision.

Which is why the same part number behaves differently on two boards, and why moving a capacitor two millimetres can matter more than doubling its value. See decoupling capacitors.

The regulator is a component too

A voltage regulator is usually modelled as an ideal source, and it is not. Two properties belong in a PDN model:

Closed-loop output impedance — approximately resistive inside the loop bandwidth and rising like an inductor above it. Modelling it as R + jωL from DC gives it an enormous apparent inductance at low frequency and invents a resonance against the bulk capacitors that no real rail has.
Load line — many high-current rails deliberately regulate to a voltage that falls with load. That halves the apparent transient excursion and reduces power at heavy load, at the cost of a DC window that is now load-dependent. Static and dynamic budgets then have to be evaluated together rather than separately.

One port is not the PDN

Everything above describes components. The last modelling gap is structural: a die has many loads and many observation points, and a single impedance at one port answers only "how much does the rail move when this block draws current?"

It does not answer "how much does a noisy block over there disturb me?" That is a transfer impedance, and on a shared plane it can be the number that matters. A rail can pass its own target and still be disturbed by a neighbour, and fixing a peak at one port can move it to another.

What to do about it

Use the vendor's bias curve, not the marking. Every major manufacturer publishes capacitance against DC bias, and most provide S-parameter or SPICE models that include it. Using them is the single highest-value correction available.

Prefer a larger case size at the same value where the space exists. The thicker dielectric derates less under bias, and often ends up delivering more real capacitance than a smaller part of a higher marked value.

Model ESR as frequency-dependent if the peaks matter. It is the damping term you control by choosing a part, which is why it gets the attention — but it is not the only one in the circuit. Plane and via resistance, the regulator's own output resistance inside its control bandwidth, the die's on-chip resistance, and dielectric loss in the plane cavity all dissipate. On a well-damped rail those can matter as much as the capacitors' ESR; on a rail with a sharp mid-band peak the capacitors usually dominate it. The useful habit is to ask which resistance is in series with the circulating current at the frequency of the peak, rather than to assume it is the one on the datasheet.

Model the mounting, not the part. For the short, wide, via-in-pad geometries this page assumes, the loop adds a few hundred picohenries to a part whose own ESL is a few hundred — so datasheet ESL alone understates the total by roughly two to three times. A long thin trace to a distant via makes it much worse than that; a part mounted directly over a via pair with a thin dielectric underneath makes it better. The factor is geometry, so measure or extract yours rather than carrying this one.

Using this to find a fault

Measured impedance consistently above simulated. Check bias derating first. It is the largest single discrepancy and it is systematic, not random.
A rail that degrades over temperature more than the silicon explains. Class II dielectric moving with temperature.
Two boards, same BOM, different peaks. Mounting, or actual capacitance under bias. Both vary; neither is on the BOM.
Anti-resonance peaks taller than modelled. Flat ESR in the model. The real ESR is lower near resonance, so there is less damping than assumed.

Go deeper — why smaller packages derate harder, and why ageing resets

Derating and dielectric thickness. Capacitance density is won by making the dielectric layers thinner, so a smaller package at the same value has thinner layers. The field across the dielectric is the applied voltage divided by that thickness — so at the same rail voltage, a smaller part sees a higher field and loses more permittivity.

The consequence is counter-intuitive and worth internalising: between two parts of the same marked value, the physically larger one usually delivers more capacitance in circuit. Choosing the smaller part to save board area can cost you the capacitance you were buying.

Why ageing resets. The ferroelectric domains in a Class II dielectric relax over time towards a lower-permittivity arrangement, which is why capacitance falls logarithmically with time. Heating the part above its Curie point randomises the domains again and restarts the clock — which reflow soldering does. So the ageing clock starts at assembly, not at manufacture, and a part measured at incoming inspection is not in the state it will be in on the board.

And the one that is not a derating at all. Class I dielectrics — C0G/NP0 — are not ferroelectric. They have essentially no bias dependence, negligible temperature coefficient and no ageing. They also have far lower capacitance density, so they appear in small values where stability matters rather than in bulk decoupling. If a model and a measurement agree suspiciously well on a rail, check whether the parts were C0G.

In the real world

This page exists because PDN simulation has a systematic bias, and the bias is always optimistic. Marked capacitance, flat ESR, datasheet ESL and an ideal regulator each flatter the design a little, and they compound.

Which makes the first question about any PDN discrepancy the same one: not "is the model wrong?" but "which of these four is the model still using the datasheet value for?" Usually at least one of them is.

Decoupling Capacitors: ESR, ESL, and Placement — the mounting loop in detail
PDN Anti-Resonance and Impedance Peaks — why ESR is the term that matters
VRM Control-Loop Bandwidth and Load Transients — the regulator's output impedance shape
Chip-Package-System Power Integrity Co-Analysis — why one port is not the PDN
Lab C: PDN Impedance, Current Sharing, and Transient Droop — the whole ladder, with branch currents

Sources

Novak et al. — DC and AC Bias Dependence of MLCC Capacitors, DesignCon East 2011 C-19

Rows marked with a claim id are tracked in the claim ledger, which records what each source can and cannot establish.