Transmission-Line Reflections and Ringing

By Geetansh Arora — Principal SI/PI Engineer12 Sep 20267 min

A signal that meets a change in impedance sends part of itself back the way it came. On a line that isn't terminated, that echo bounces between the driver and the load — again and again — until the losses finally kill it.

Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.

1 V step into a 3-inch stripline · T_d = 500 ps analytical Γ_s — Γ_L — launched — overshoot —

Voltage along the line — watch the wave travel and bounce

total voltage forward wave reflected wave

Voltage vs time — drag to scrub

at load at driver settled value

Bounce diagram — position across, time down

travelling to the load travelling back

Driver impedance R_s10 Ω

Output impedance of the buffer

Line impedance Z₀50 Ω

Set by stackup and trace geometry

Load R_L∞ (open)

open circuit (a CMOS input pin)

Rise time t_r80 ps

Slow it past 2T_d = 1000 ps and the ringing hides

edge launched · t = 0 —

What you see on the scope

Before the physics, the symptom. You probe a net at the receiver and expect to see a clean 0-to-1 V step. Instead the waveform overshoots to 1.6 V, dips back to 0.7 V, bounces up again, and after a few cycles settles to the 1 V it was supposed to reach. That staircase is ringing, and it is the single most recognisable waveform defect in digital board design.

Ringing is not random noise. It is a signal bouncing back and forth between the two ends of a trace, like a ball between two walls. Each bounce is smaller than the last — the driver absorbs some of the energy on every return trip — but the first overshoot can be large enough to damage an input, trip an ESD clamp, or violate a timing spec. The rest of this page explains why it happens and how to predict its amplitude.

What is actually happening

Here is the thing that makes reflections click: the driver has no idea what is at the far end of the line. When the buffer switches, the edge starts travelling down the trace at roughly half the speed of light, and it will not reach the load for another 500 picoseconds. It has to decide how much voltage to launch right now, with no information about the load whatsoever.

So it does the only thing it can. It sees the line's characteristic impedance — 50 Ω, in the panel above — and treats it as if it were a 50 Ω resistor to ground. A 10 Ω driver into a 50 Ω line is just a voltage divider: it launches about 833 mV of the 1 V swing, and that packet of voltage sets off down the trace.

Half a nanosecond later it arrives at the load and finds an open circuit — a CMOS input pin is, to a first approximation, no load at all. Now there is a contradiction. The wave is carrying 833 mV and 16.7 mA of current, but an open circuit cannot accept any current. The only way to satisfy both the line and the load is to launch a second wave back toward the driver, one that exactly cancels the incoming current — and that reflected wave carries another 833 mV with it. Which is why the voltage at the load momentarily jumps to 1.67 V, well above the rail it was supposed to reach.

That echo now travels back, and 500 ps later it reaches the driver — which is a 10 Ω source, also not a match for 50 Ω. So it reflects again, this time mostly inverted, and heads back to the load. Each round trip the amplitude shrinks by the product of the two reflection coefficients, and the voltage staircases its way toward the value it should have had all along. Drag the scrubber on the middle panel and you can watch each step land, one every 2T_d.

The part that costs you silicon Compare the 1.67 V overshoot with the receiver's specified AC limit and allowed duration. Repeated excursions outside that envelope can affect reliability, while an undershoot or secondary crossing can consume noise margin or create an unintended transition.

Three ways to control reflections

Every termination scheme is the same idea wearing different clothes: make one end of the line look like the line. Kill either reflection coefficient and the echo has nowhere to go.

Series termination. Add resistance at the driver until R_s = Z₀. The wave still reflects off the open load, but when it gets home it is absorbed instead of bounced. Costs one resistor and no DC power — which is why it is everywhere on low-speed control nets. Try the preset: the waveform steps up once and stops.
Parallel termination. Put Z₀ to ground at the load. Now nothing reflects in the first place and the waveform is clean from the first edge — but you burn DC current the whole time the line sits high.
Use no added termination when the route is electrically short. If the edge is slow compared with the round trip, the reflections come home while the driver is still switching and simply blend into the edge. Push the rise-time slider past 1000 ps and watch the ringing dissolve.

Use the impedances at the physical endpoints For a source termination, include the driver's output impedance, package, and added resistor; their sum is what the returning wave sees. For a parallel termination, include the receiver input and the connection between the resistor and pad. A resistor with the right printed value can still be the wrong termination when a via or stub separates it from the endpoint.

Go deeper — the maths, the numbers, and where the rules of thumb break

Everything above falls out of one equation. At any interface between an impedance Z₂ and the line it sits on, the fraction of the incident wave that comes back is:

Γ = ( Z₂ − Z₀ ) / ( Z₂ + Z₀ ) Γ = +1 at an open (Z₂ → ∞), −1 at a short (Z₂ = 0), and exactly 0 when Z₂ = Z₀. Γ is bounded by ±1 for any passive load.

And the amount the driver launches in the first place is a plain resistive divider against the line, not against the load:

V_inc = V_s · Z₀ / ( R_s + Z₀ ) With Vs = 1 V, Rs = 10 Ω, Z₀ = 50 Ω: 833 mV. The load never enters this expression.

The voltage sitting at the load right after the first reflection is the incident wave plus its own echo, which is where the 1.67 V comes from:

V_load(T_d) = V_inc · ( 1 + Γ_L ) = 833 mV × 2 = 1.67 V Every subsequent step is smaller by a factor of Γ_L·Γ_s, arriving one round trip (2T_d) apart.

When does this matter?

The industry rule of thumb is that reflections become a problem when the round-trip delay is a meaningful fraction of the rise time — commonly stated as:

terminate when 2T_d > t_r / 3 Equivalently: a trace becomes "long" past roughly t_r / (6 · propagation delay per unit length).

Where that rule is insufficient. It assumes a single driver, a single receiver, and a uniform line. Extend the analysis for:

Multi-drop nets. Every stub is another discontinuity with its own Γ. The round-trip rule alone does not describe a resonant T-branch.
Loads that aren't resistive. A real CMOS input is a few pF, not an open. The reflection coefficient becomes frequency-dependent, and the sharp corners in the panel above become rounded in silicon.
Long lossy channels. Past a couple of GHz the line attenuates the echo faster than the reflection coefficients do. Above ~10 dB of insertion loss the reflections mostly bury themselves — but by then loss and ISI are your problem instead.

The three schemes, side by side

Scheme	Γ killed	DC power	Signal at load	Typical use
Series (source)	Γ_s → 0	none	full swing, one step	reset, control, slow GPIO
Parallel to ground	Γ_L → 0	V²/Z₀ when high	set by the source/load divider, not by the termination	rarely alone
Thevenin (split)	Γ_L → 0	continuous	full swing, biased	legacy DDR address/command
On-die (ODT)	Γ_L → 0	gated per burst	full swing	LPDDR5X, PCIe, USB, UFS

Modern high-speed interfaces have almost entirely moved the termination on-die, which is worth understanding as an SI decision and not just a packaging one: a resistor on the board sits a via and a stub away from the actual receiver, and at 8533 MT/s that parasitic inductance is enough to undo most of what the termination was supposed to buy you. Putting it inside the pad removes the stub — and lets the controller switch it on only during a read burst, which is the only reason the power budget survives.

In the real world

Reflections are a useful early hypothesis when a net misbehaves, and source damping is often inexpensive. They can also be designed in and then discovered at bring-up, because a schematic gives you no hint that a trace is electrically long. Fast data buses usually receive careful transmission-line analysis, while a reset line routed 8 inches across the board to four loads may receive less attention. With an uncharacterised buffer, that line can arrive with 400 mV of ringing near the receiver's threshold.

The practical sign-off habit: before worrying about eye diagrams, sweep the driver corner. A fast- strong process corner has a lower R_s and a faster t_r than the typical model — both of which make reflections worse. A net that passes at typical and fails at fast-strong is the classic reflection signature, and you can spot it in the panel above by dragging R_s down and t_r left at the same time.

Open, short, matched, and resistive line reference experiments — saved Lab A cases with analytical boundary values and tolerances
When does a trace become a transmission line?
Transmission-Line Characteristic Impedance
Transmission-Line Termination Schemes
LPDDR5X sign-off: ODT and driver strength training