Lab D: ADC Interference, Aliasing and Reference Noise

By Geetansh Arora — Principal SI/PI Engineer18 Sep 202618 min

An analog-to-digital converter compares a voltage with its reference at instants its clock defines, so anything coupled onto the input or the reference at those instants becomes part of the code — and sampling, not the aggressor, decides where in frequency that error lands.

On modern mixed-signal circuit boards, high-speed digital processors live mere millimetres away from sensitive analog-to-digital converters (ADCs). Microcontroller GPIOs, memory buses, and high-frequency switch-mode power supplies constantly inject picosecond current spikes into shared ground planes and adjacent traces.

When high-frequency digital noise couples into an analog front-end, intuitive circuit thinking suggests the noise should remain at its original frequency — for example, a 100 MHz clock harmonic staying safely at 100 MHz, far above an audio or sensor bandwidth. In a sampled system, however, this intuition fails. The ADC's sampling clock acts as a mathematical mixer: any noise present on the input or reference rail at the precise sampling aperture is folded (aliased) directly down into the baseband. A 100.001 MHz clock harmonic can fold into the audio band as a piercing 1 kHz tone that no digital filter can distinguish from true signal.

Furthermore, how that interference behaves depends fundamentally on the converter's internal architecture. A Successive Approximation Register (SAR) converter makes instantaneous bit decisions across multiple clock ticks, making it acutely vulnerable to reference rail droop during specific bit trials. An oversampling Delta-Sigma (ΔΣ) modulator shapes quantization noise and relies on decimation filters, creating deep attenuation notches that can completely swallow an aggressor — or allow it to alias catastrophically if it falls near the modulator clock.

What this page does, and how to use the lab

Every board that measures something has digital signals switching near its analog-to-digital converter — GPIOs, clocks, serial buses — and a little of that switching always couples in. What matters is what it does once inside: a spur, lost SNR, an offset that will not calibrate out. That depends as much on the converter and its clock as on the aggressor.

The lab below lets you build that situation and watch the result. It simulates a SAR and a second-order Delta-Sigma converter sample by sample, with one aggressor you shape and couple in, and measures the output the way a converter test would. Change any control and every plot answers together.

Along the top: the resultsSNR, the SNR lost to the aggressor, SFDR and offset.
Left: the aggressorScenarios, then its frequency, clock, swing and edges, and how it couples in.
Middle: what happensThe output spectrum, spurs labelled by the harmonic behind them, and the folding map tracing each harmonic to where it lands.
Right: the converterSAR or Delta-Sigma, resolution or oversampling, full scale, noise and test tone.
Below the plots: more viewsThe disturbance in time, SNR swept against aggressor frequency, the modulator's full band, and every value as text.

A good way to start

Open a scenario. Choose Folds into band on the left, read its note, and find its spur in the spectrum; the folding map's dashed line leads back to the harmonic that made it.
Predict, then change one thing. Say what you expect before you move a control — where the spur goes, whether SNR falls — then check the numbers along the top.
Swap the converter. Change the architecture on the right. The aggressor stays as it was, so any difference belongs to the converter.
Take the guided tour. Guided, at the top right of the lab, asks a question at each step and sets the lab up for it.

Along the way Point at a control and the line under the plots says what it changes. Hover over a plot to read its values, or expand it to fill the frame. Values can be typed with their units, such as 4.1273 MHz or 500 ps. Pin A freezes the current result so a change shows against it, and Verify lists what the model includes and what it leaves out.

The lesson below the lab explains the physics behind everything the lab shows.

Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.

One aggressor · two converters numerical SNR— lost to the aggressor— SFDR— offset—

Aggressor what couples in

Scenarios · SAR

Aggressor

Shares the converter's clock

Off, the default: the aggressor runs from its own oscillator, like a GPIO or a nearby interface, and knows nothing of the converter's clock. On: it is timed from the same crystal, as PWM or SPI from the microcontroller that clocks the converter can be, so its ratio to the converter clock is exact.

Frequency

Drag, or type a value with its unit: 4.1273 MHz, 51 Hz, 128k.

Frequency errorppm

The aggressor's error against the converter's crystal. Two oscillators never agree exactly: at a nominal match the aggressor beats at this fraction of its frequency, and 20 ppm of 1 MHz is 20 Hz.

A multiple of

A multiple of the output data rate lands on the sinc³ filter's nulls; a multiple of the modulator clock folds straight to DC.

Multiple×

Every harmonic of an exact multiple is also an exact multiple, so all of them land in the same place.

Phase°

Where the aggressor is at every sample. With a shared clock the error is the aggressor's value at this phase, so it sets the offset.

SwingV

The aggressor's logic swing, peak to peak, before coupling. Its mean is left out: a DC shift is an offset you would calibrate.

Rise/fall time

10–90%. Held to a fifth of the aggressor's period, so the range follows its frequency: up to 200 ns at 1 MHz, 2 ns at 100 MHz. Faster edges carry harmonics further.

Coupling

Into

Into the input, a disturbance adds. Into the reference, it multiplies: the code is the input divided by the reference.

Mechanism

Flat: a shared impedance passes every harmonic at one ratio. Capacitive: coupling follows the rate of change, so faster edges and higher harmonics arrive larger.

LeveldB

Voltage ratio from the aggressor to the pin. For capacitive coupling, the ratio at 1 MHz.

RC bandwidth

One RC pole between the aggressor and the pin: the filter at the input, or the reference's decoupling. Harmonics above it are attenuated before the converter samples them, so they cannot fold.

Output spectrum

Folding map

Frequency axis

Disturbance in time

SNR against aggressor frequencysweep

Modulator full band

Converter what samples it

Converter

Architecture

Switching keeps the aggressor, so the same disturbance can be compared on both converters.

Resolutionbits

Ideal quantization SNR is 6.02 dB per bit plus 1.76 dB, for a full-scale sine.

Sample rate

Every frequency folds into 0 to half of this. Exact multiples of it fold to DC.

Modulator clock

The rate the loop samples at. An aggressor near a multiple of it folds straight into the band before any filter runs.

Oversampling ratio

Each doubling moves the output data rate down an octave and buys about 15 dB of quantization SNR for a second-order loop.

Full scale

The reference. A larger full scale makes the same coupled millivolts a smaller fraction of it.

Input noiseµV rms

White noise at the input on every sample, such as kT/C: 20.4 µV rms for 10 pF at 300 K.

Input tone

Frequency

Moved to the nearest frequency with an odd number of cycles in the record, so the tone sits exactly on a bin.

AmplitudedBFS

Reference coupling scales with this; input coupling does not. A 1-bit Delta-Sigma loop overloads near full scale and is refused there.

Learning sequence

Predict

A 4 MHz clock couples into a 1 MS/s SAR. Where in the output spectrum does it appear, and does locking it to exactly 4 × the sample clock make it harmless?

Experiment

Run Folds into band, then Locked at 4 × clock, then …50 ppm apart. Watch SNR, the offset and where the spur sits.

Explain

Sampling folds every harmonic to its distance from the nearest multiple of the clock. An exact multiple folds everything to DC, which SNR excludes and offset reports; two oscillators are never exact.

Transfer

A 10 Hz Delta-Sigma must live beside a 51 Hz square wave. Name two changes that would each remove its spur, and say which one also protects against a 60 Hz neighbour.

Two ways to turn a voltage into a number

Both converters in the lab do the same job — they decide which of 2^N codes best describes a voltage — but they spend their time very differently, and that difference decides which interference hurts each of them.

Where interference enters · red marks the input, the reference and the clock

SAR — one sample, N decisions

Delta-Sigma — many coarse samples, then a filter

A SAR converter samples once, then searches. A switch and a capacitor hold the input still, and the logic asks N questions about it, most significant first: is the input above half of full scale? Above three quarters? Each question sets a DAC to a trial code and compares, and each answer fixes one bit. The DAC's voltage is the trial code times the reference, so the reference is read N times per conversion, once per question — each at a slightly different moment.

A Delta-Sigma converter samples fast and coarsely, then averages. Its modulator is a feedback loop around a quantizer with only two levels. It integrates the difference between the input and what it last fed back, and chooses +V_ref or −V_ref to keep that integral near zero, so the average of the bitstream follows the input. The error of a two-level quantizer is enormous on every sample, but the loop pushes it towards high frequencies, where a digital filter removes it while lowering the rate by the oversampling ratio. The lab's loop is second order, with a sinc³ filter.

	SAR	Delta-Sigma
Conversion	one sample, then N comparisons against a reference-scaled DAC	many 1-bit samples in a feedback loop, then a digital filter
Resolution comes from	DAC matching, comparator noise and the sampling capacitor's noise	the oversampling ratio and the order of the noise shaping
Time to a result	one conversion	the filter's length: three output samples for sinc³
Switching between inputs	natural — every sample stands alone	slow — the filter settles again after every switch
Anti-alias filtering	needed for everything above f_s/2	needed only near multiples of the modulator clock
Reference disturbance	read at every bit decision	scales the feedback, and mixes with shaped quantization noise
“Safe” interference frequency	exact multiples of f_s, which fold to DC and become offset	exact multiples of the output data rate, where the filter has nulls

Sampling decides where the error lands

A clock coupled at 4 MHz can hurt a converter whose band ends at 500 kHz, because a sampler cannot tell two frequencies apart once they produce the same samples. A tone sampled at f_s is indistinguishable from a tone at its distance to the nearest multiple of f_s: 4.1273 MHz sampled at 1 MS/s looks exactly like 127.3 kHz. A clock is a square wave, so it is not one tone but a series — the odd harmonics, each smaller in proportion to its number — and every harmonic folds on its own. That is the spread of spurs in Folds into band.

Before you run Shared clock 4×, predict what an exact multiple does. If every sample catches the aggressor at the same point in its cycle, every sample sees the same error, which is a constant. The spectrum comes back clean and SNR returns to its ideal value, because SNR leaves DC out — but the output has moved by the aggressor's value at that phase: 0.90 mV, or 11.8 LSB. The interference did not go away. It became offset.

But an exact multiple needs a shared clock, and most aggressors — a GPIO, a nearby interface — run from oscillators of their own and know nothing of the converter's. Two oscillators never agree exactly. In GPIO at 1 MHz the aggressor sits 20 ppm off a 1 MS/s converter, so its fundamental beats at 20 Hz. That is slower than the lab's 65.5 ms record can resolve, so it lands in the DC bins and reads as offset — an offset that wanders in any real measurement — while its harmonics land at 100, 140 and 180 Hz, where slow, precise measurements live. The frequency that looked safest puts the interference closest to DC. The lab treats every aggressor this way unless you tick Shares the converter's clock.

Edge rate decides how far the series reaches. A trapezoid's harmonics fall at 20 dB per decade up to 0.8/(πt_r), where t_r is the 10–90% rise time of a linear edge, and at 40 dB per decade beyond it: 255 MHz for 1 ns, 25 MHz for 10 ns. Through a flat coupling path the fundamental dominates, and the edge barely matters. Through a capacitor the coupled voltage follows dV/dt, so each harmonic arrives larger than it otherwise would until the edge rolls the series off. Compare Slow edges with Fast edges: 7.2 dB of SNR from edge rate alone.

The input adds; the reference multiplies

On the input, a disturbance simply adds to the signal, and its spurs do not depend on how large the signal is. On the reference it multiplies. The code is the input divided by the reference, so a small fractional ripple δ on the reference becomes an error of −δ times the input: a pair of sidebands around the input tone that scale with it. Halve the input and the sidebands fall 6.02 dB with it, so SNR does not improve. Only a quieter reference helps.

A SAR reads its reference at every bit decision, so a disturbance that is quiet at the sampling instant still corrupts the code if it arrives during the search. A Delta-Sigma reads it on every modulator sample, where it multiplies a bitstream full of shaped quantization noise. Ripple near half the modulator clock takes the noise the loop pushed furthest away and shifts it back down to DC. In Ripple on V_ref no spur appears at all, yet SNR falls from 90.1 to 72.2 dB.

What the error becomes: offset, gain and linearity

Beside SNR the lab reports offset: the average of every output sample in the record. The input sine completes a whole number of cycles in the record, so it averages to exactly zero, and the model's converter has no offset of its own — whatever offset you see, the aggressor put there. It is reported on its own because SNR leaves the DC bins out, so an error that lands on DC does not lower SNR at all.

An aggressor whose error lands inside the band rises and falls many times within a record and averages away; it costs SNR instead. An aggressor that shares the converter's clock is different. Its error repeats identically on every conversion, so it behaves like a flaw in the converter itself — and which flaw depends on where it couples and when it arrives. For the 16-bit SAR at 1 MS/s, with a 1.8 V aggressor sharing its clock at exactly 1 MHz:

Coupling	What every conversion sees	What it becomes	In the model
Into the input, −40 dB	the same voltage added to every sample	Offset error: the whole transfer curve shifts	offset +9.0 mV, which is 118 LSB of 76.3 µV; the tone's level and its distortion unchanged
Into the reference, −20 dB, phase 180°: every bit trial sees the same level	every decision threshold scaled by one factor	Gain error: the transfer curve tilts	the tone reads −0.68 dBFS instead of −1.00 dBFS, as if the reference were 2.41 V; no offset, no added distortion
Into the reference, −20 dB, phase 270°: an edge arrives during the bit trials	the early bits and the late bits decided against different references	Nonlinearity: the mechanism behind DNL and INL — shown here as distortion, not measured as a static spec	THD rises from −126.5 dB to −53.5 dB and SINAD falls from 97.1 dB to 47.6 dB; no offset

The first two are not linearity errors. INL is measured against a straight line through the transfer curve, after offset and gain have been removed, so a curve that is shifted or tilted but still straight has none. The third is one, because a SAR decides its bits one at a time, each against a DAC scaled by the reference at that moment. Change the reference partway through a conversion and the bits decided before the change are weighed differently from those decided after it, exactly as if the DAC's bit weights were mismatched. The errors gather at the major code transitions, where many bits change at once, and they repeat with the bit pattern — the signature an unsettled reference leaves in a DNL plot. The lab runs no static ramp test, so it shows the same flaw the way a spectrum does, as distortion: with the aggressor 40 dB down, SINAD still falls to 52.5 dB.

Be careful with that last step, because it is the one most easily overstated. DNL and INL are named here as the mechanism, not as measurements: they are defined on a static transfer curve, extracted from code transitions over a slow ramp against a straight line, and this lab never runs that test. THD is not a substitute for it. The two only look alike while the disturbance repeats in step with the conversions — a reference error that is different on every conversion is not a static nonlinearity at all, however much distortion it produces, which is exactly what the next paragraph is about.

An aggressor on its own oscillator repeats nothing. Near a multiple of the clock its error drifts at the beat frequency, so a DC measurement sees an offset that wanders: GPIO at 1 MHz reads anywhere between −0.21 and +0.21 mV, depending on where the aggressor is when the record starts. A histogram test of INL sees its code bins smeared differently every time. Static specifications assume an error that repeats, and an independent aggressor never does.

A Delta-Sigma converter follows the same logic for offset and gain. Its feedback DAC has only two levels, so it has no bit weights to mismatch and no DNL in the SAR's sense; reference ripple that correlates with the bitstream appears instead as noise and distortion that change with the input level. That mixing is a property of this loop — discrete-time, second order, one bit, with the reference multiplying the feedback directly. A continuous-time modulator, a multi-bit feedback DAC or a different decimator will move the result; read the mechanism here, not a number to expect from a particular part.

See all three Tick Shares the converter's clock, set the multiple to 1 and couple into the input at −40 dB: the offset appears and SNR does not move. Couple into the reference at −20 dB with the phase at 180° and read the input tone's level in Values as text. Then move the phase to 270°: SINAD and SFDR fall, and the offset stays at zero.

What the Delta-Sigma filter can and cannot remove

The sinc³ filter has a null at every multiple of the output data rate, so a 10 Hz output rate nulls 50 Hz and 60 Hz at once. For a sine the null is narrow: 51 Hz is still rejected by 103 dB, but 55 Hz by only 74 dB. For a square wave the null holds only for the harmonics that stay on it. In On the notch a 50 Hz square wave 20 ppm off sits 1 mHz from its null, yet costs 2.9 dB: harmonic n sits n mHz from its own null, and far enough up the series that is inside the passband.

One hertz further and the damage is of a different kind. In …1 Hz off it a 51 Hz square wave costs 16.4 dB of SNR, and the filter's skirt has nothing to do with it: the square wave's 251st harmonic, at 12,801.3 Hz, sits 1.26 Hz from five times the 2.56 kHz modulator clock. The modulator samples it as 1.26 Hz before the filter runs, and a filter cannot reject what it is shown as signal. Anything near a multiple of the modulator clock behaves the same way: Near the clock puts an aggressor 20 ppm from the clock at 5.12 Hz, inside the band.

Why the lab's modulator clock is slow The lab caps the oversampling ratio at 256 so that a run stays interactive, which puts the modulator clock for a 10 Hz output rate at 2.56 kHz. A converter that oversamples further has a faster modulator clock, and the harmonics that fold near its multiples are higher and weaker — but the mechanism is the same, and so is the fix.

Go deeper — what the lab measures, and the algebra behind it

What SNR counts here

SNR is the fundamental's power over everything else in the band except its harmonics 2 to 6 and DC. Interference counts as noise, because to a measurement it is. SINAD includes the harmonics, ENOB is SINAD referred to full scale, and SFDR compares the fundamental with the largest single spur. The spectrum uses a 4-term Blackman–Harris window and sums each tone over ±4 bins, so a spur that falls between bins is still measured at its full power.

SNR_ideal = 6.02·N + 1.76 dB Quantization alone, for a full-scale sine: 98.1 dB at 16 bits. The lab's SAR input sits 1 dB below full scale, so 97.1 dB.

SQNR ≈ 6.02 + 1.76 − 10·log₁₀(π⁴/5) + 50·log₁₀(OSR) dB A second-order loop with a 1-bit quantizer, in the linear model: 85.2 dB at an oversampling ratio of 64, and 15.05 dB more for every doubling. A real 1-bit loop measures a few dB under the model — 4.1 dB in the lab at 128.

The fold

f_out = | f − round(f / f_s)·f_s | 4.1273 MHz at 1 MS/s lands at 127.3 kHz. For a Delta-Sigma, fold by the output data rate and scale by the filter's response at the original frequency.

A clock's harmonics

|c_n| = (2A / nπ) · | sin(nπt_e/T) / (nπt_e/T) | Odd n only, for a 50%-duty trapezoid of A peak to peak whose linear edges each last t_e = t_r/0.8, for a 10–90% rise time t_r. A 1.8 V swing has a 1.146 V fundamental; coupled 80 dB down that is 114.6 µV, −86.8 dBFS on a ±2.5 V converter. The lab's 20 MHz path pole takes another 0.2 dB, so it reads −87.0 dBFS.

The sinc³ response

|H(f)| = | sin(πf/f_ODR) / (OSR·sin(πf/f_mod)) |³ Zero at every multiple of the output data rate except the multiples of f_mod, where it returns to one. At a 10 Hz output rate and an oversampling ratio of 256: −102.9 dB at 51 Hz and −74.2 dB at 55 Hz.

Reference coupling

code ∝ V_in / (V_ref(1 + δ)) ≈ (V_in / V_ref)·(1 − δ) With V_in = a·sin ω_int and δ = d·cos ω_at, the error is two sidebands at ω_in ± ω_a, each a·d/2 — proportional to the input.

The second-order loop's noise transfer function is (1 − z⁻¹)². Its magnitude is 4 at half the modulator clock — 16 times the power of plain quantization noise — and close to zero in the band. Multiplying the bitstream by ripple 7 Hz below half the clock moves that peak to within 7 Hz of DC.

The noise the lab can add

v_n = √(kT / C) A sampling capacitor's own noise: 20.4 µV rms for 10 pF at 300 K. The lab's input noise control adds white noise of this kind to every sample.

What the model leaves out

Clock jitter and aperture uncertainty; supply and ground bounce as paths of their own; DAC mismatch and nonlinearity; continuous-time and multi-bit modulators; and any anti-alias filter beyond a single pole. Each of these moves the numbers. None of them changes where a folded tone lands.

In the real world

Treat the reference as a signal. A SAR reads it at every bit decision, so its decoupling has to hold it still through the whole conversion, not only at the sampling instant. A Delta-Sigma turns ripple near half its modulator clock into noise. Keep aggressors, and the paths their return currents take, away from the reference and its capacitor.

Lock only what stays locked. Deriving a noisy clock from the converter's own clock turns its harmonics into offset instead of spurs, and offset can be calibrated out. But only a shared oscillator gives an exact ratio: two crystals at nominally the same frequency are the case that hurts most.

Slow the edges you do not need. Near a converter, a series resistor on a clock or data line gives up edge rate that line may not need and removes harmonics that would otherwise fold into the band. Under capacitive coupling, edge rate matters as much as amplitude.

Choose the output data rate on purpose. A Delta-Sigma's nulls sit at multiples of its output data rate, and 10 Hz nulls both 50 Hz and 60 Hz. The nulls are narrow, and they do nothing for a harmonic that lands near a multiple of the modulator clock. A spread-spectrum clock spreads each harmonic over a band: it lowers a spur's peak, but the power still counts against SNR.

Measure the way the lab does. Coherent sampling puts the input exactly on a bin, a window handles the aggressor that will not be coherent, and SNR, SFDR and offset each answer a different question. An aggressor at an exact multiple passes an SNR test and fails an offset one.

Sources

Rows marked with a claim id are tracked in the claim ledger, which records what each source can and cannot establish.

Where this is explained

This page is the instrument. The mechanisms it lets you change are described on the topic pages below, each one linked for the specific thing it explains rather than as a general reading list.

Crosstalk — how an aggressor reaches a victim net, which is the coupling this lab applies.
Signal Bandwidth: Why Edge Rate Matters — why a slow clock still carries energy near the sampling frequency.
Ground bounce and SSN — switching current in a shared return, the usual path onto a reference.
Jitter taxonomy — uncertainty in the sampling instant, which this lab holds fixed.