# Claim ledger — protocol and specification statements

**Generated from [`claims.json`](claims.json) by `python3 scaffold.py claims`.**
Edit the JSON, not this file.

Every claim on this site that rests on a **specification** rather than on first
principles belongs here, with the source it needs, the conditions it assumes,
who checked it and when. Numbers derivable from physics are handled instead by
`check-numbers.py`, which recomputes them.

## What a source type means

| type | means | can verify |
|---|---|---|
| `normative` | a requirement in a named standard | only by reading that standard |
| `public-rate` | a data rate the standards body has published openly | itself, and nothing electrical |
| `vendor` | an implementation guide or application note | how somebody implemented it |
| `commercial` | a supplier capability, not a standard | what suppliers offer |

A **normative** claim cannot be marked verified from a rate announcement, an
application note or a datasheet. `scaffold.py check` enforces that, so the
distinction cannot quietly erode.

## Status

| | |
|---|---|
| **verified** | read against the cited source, with who checked it and when recorded. This is a SOURCE check, and on every current row it was done by the model, not by a person - see the owner / sourceCheckedBy / humanReviewedBy split |
| **scoped** | wording narrowed so it no longer asserts more than is known |
| **awaiting** | stated on the page and not yet checked against its source |

**34 claims: 11 verified, 21 scoped, 2 awaiting a source.**

Compound claims are split, because verifying one half used to verify the whole
row. "Gen 4 is 28 dB and Gen 5 is 36 dB" is two budgets against two editions;
"FLIT-only with FEC and CRC and replay" is four mechanisms doing different jobs.

## Ledger

| # | Claim | Pages | Source needed | Type | Status | Reviewed |
|---|---|---|---|---|---|---|
| C-1 | Data bus inversion reduces the number of simultaneously switching outputs on an LPDDR5X data byte. | `power-integrity/ssn-ground-bounce` | JESD209-5x, DBI mode definitions | `normative` | **scoped** — Wording now distinguishes transition-minimising from level-minimising inversion and claims no universal 50% bound. | — |
| C-2a | LPDDR5X reaches 8533 MT/s. | `interfaces/lpddr5x` | JEDEC press release, "JEDEC Updates Standard for Low Power Memory Devices: LPDDR5" | `public-rate` | **verified** — JEDEC’s own announcement of JESD209-5B states the speed extension to 8533 Mbps. Verifies that the family reaches this rate; says nothing about which speed bin a given part supports, or about the electricals. JESD209-5C (July 2023) is the current revision and is downloadable from jedec.org after registration. | — |
| C-2b | LPDDR5 reaches 6400 MT/s. | `interfaces/lpddr5x` | JEDEC press release, "JEDEC Updates Standard for Low Power Memory Devices: LPDDR5" | `public-rate` | **verified** — The same announcement gives 6400 Mbps as the previous revision’s ceiling, which is the LPDDR5 figure. Verifies the rate, not any particular device’s bin. | — |
| C-3 | An LPDDR5X channel is normally point-to-point, controller to DRAM, with no connector and no fly-by topology — but a dual-rank or two-die configuration puts more than one device on the same data net. | `interfaces/lpddr5x` | Synopsys LPDDR5 technical bulletin and LPDDR5X/5/4X controller documentation, on rank and dual-channel support; byte-mode descriptions of two 8-bit dies on one 16-bit channel | `commercial` | **scoped** — Corrected. "Point to point rather than multidrop" was too strong: LPDDR5 defines non-target ODT precisely because a dual-rank configuration exists, and a device may be built as two 8-bit dies sharing one 16-bit channel. The page already says so — it calls "never multi-drop" a step too far and tells the reader to check the configuration — so this row now matches what the page claims rather than what it used to. | — |
| C-4a | WCK is the write data clock on LPDDR5X. | `interfaces/lpddr5x` | Synopsys LPDDR5 technical bulletin, on the WCK and RDQS forwarded clocks | `commercial` | **scoped** — Confirmed: LPDDR5 introduces two unidirectional strobes, WCK for writes and RDQS for reads, with WCK forwarded at two or four times the CK rate. Scoped rather than verified because the ratio options and their training are in JESD209-5, which has not been read. | — |
| C-5 | Read and write training centre the strobe in the data eye. | `interfaces/lpddr5x` | JESD209-5x training sequences | `normative` | **scoped** — Narrowed: training also adjusts ODT, drive strength and reference levels, so 'training centres the eye' is one of several things it does. The panel labels its training model illustrative. | — |
| C-6a | A PCIe Gen 4 channel insertion loss budget is about 28 dB at 8 GHz. | `interfaces/pcie-gen4-gen5`, `signal-integrity/channel-budgeting` | Texas Instruments SNLA426, high-speed PCB layout for PCIe Gen 5; Astera Labs in Electronic Design, on managing the PCIe 5.0 channel insertion loss budget | `commercial` | **scoped** — The number is only meaningful with its frequency, and the sources supply it: 28 dB at 8 GHz for Gen 4. Independent design guidance agrees on the figure. Scoped rather than verified because the reference PLANE — what the budget is measured between — is defined in the Base and CEM specifications, and that is what decides whether a given measurement can be compared with it. | — |
| C-6b | A PCIe Gen 5 channel insertion loss budget is about 36 dB at 16 GHz. | `interfaces/pcie-gen4-gen5`, `signal-integrity/channel-budgeting` | Texas Instruments SNLA426, high-speed PCB layout for PCIe Gen 5; Astera Labs in Electronic Design, on managing the PCIe 5.0 channel insertion loss budget | `commercial` | **scoped** — The number is only meaningful with its frequency, and the sources supply it: 36 dB at 16 GHz for Gen 5. Independent design guidance agrees on the figure. Scoped rather than verified because the reference PLANE — what the budget is measured between — is defined in the Base and CEM specifications, and that is what decides whether a given measurement can be compared with it. | — |
| C-7 | Gen 5 designs commonly backdrill long via stubs. | `interfaces/pcie-gen4-gen5` | none — channel-dependent practice | `commercial` | **scoped** — Treated as an implementation remedy, never a specification requirement. | — |
| C-8a | PCIe 6.0 uses FLIT mode. | `interfaces/pcie-gen6` | Synopsys, "PCIe 6.0 Verification of FEC and CRC"; Cadence PCIe 6.0 electrical testing white paper | `commercial` | **scoped** — IP vendors implementing the specification describe the 256-byte FLIT carrying TLP payload, an 8-byte CRC and a 6-byte FEC, with a lightweight single-symbol-correcting FEC backed by CRC and replay. That supports FLIT mode as a mechanism. The normative requirement and its exact field layout need the Base specification. | — |
| C-8b | PCIe 6.0 applies forward error correction. | `interfaces/pcie-gen6` | Synopsys, "PCIe 6.0 Verification of FEC and CRC"; Cadence PCIe 6.0 electrical testing white paper | `commercial` | **scoped** — IP vendors implementing the specification describe the 256-byte FLIT carrying TLP payload, an 8-byte CRC and a 6-byte FEC, with a lightweight single-symbol-correcting FEC backed by CRC and replay. That supports forward error correction as a mechanism. The normative requirement and its exact field layout need the Base specification. | — |
| C-8c | PCIe 6.0 applies a CRC with link-level replay. | `interfaces/pcie-gen6` | Synopsys, "PCIe 6.0 Verification of FEC and CRC"; Cadence PCIe 6.0 electrical testing white paper | `commercial` | **scoped** — IP vendors implementing the specification describe the 256-byte FLIT carrying TLP payload, an 8-byte CRC and a 6-byte FEC, with a lightweight single-symbol-correcting FEC backed by CRC and replay. That supports a CRC with link-level replay as a mechanism. The normative requirement and its exact field layout need the Base specification. | — |
| C-9 | PCIe 6.0 tolerates a raw error rate near 1e-6 and delivers about 1e-12 after correction. | `interfaces/pcie-gen6` | Cadence PCIe 6.0 electrical testing white paper; PCI-SIG figures as reported by EDA and test vendors | `commercial` | **scoped** — The 1e-6 raw and 1e-12 delivered figures are consistently reported as the PAM4 versus NRZ framing behind the FEC decision. Reported by implementers rather than read from the specification, so the page presents them as the design intent and not as a requirement. | — |
| C-10 | A Gen 6-capable link uses FLIT mode at lower rates as well. | `interfaces/pcie-gen6` | Cadence, "Unravelling PCIe 6.0 FLIT mode challenges"; Synopsys PCIe 6.0 design material | `commercial` | **scoped** — Confirmed with the mechanism behind it: 256-byte FLITs are supported at 2.5, 5, 8, 16 and 32 GT/s for backward compatibility, negotiation happens through the FLIT Mode Supported bit in the TS1 Data Rate Identifier during link training, and once enabled a speed change to a lower rate stays in FLIT mode. IP vendors implementing it, not the Base text. | — |
| C-18 | PCIe Gen 4 and Gen 5 define eleven transmitter presets, P0 to P10. | `interfaces/pcie-gen4-gen5` | Tektronix, "10 Things to Know about PCIe"; Synopsys PCIe 5.0 technical bulletin | `commercial` | **scoped** — Vendor test and IP documentation consistently gives eleven transmitter presets, P0 to P10, for Gen 3 onwards. The preset TABLE — the preshoot and de-emphasis each one defines — is in the Base specification and has not been read, so the page states the count and the mechanism, not the values. | — |
| C-11 | The PAM4 links in common use pair it with forward error correction. | `signal-integrity/nrz-vs-pam4` | would need the standards set defined and each one checked | `normative` | **scoped** — Narrowed from 'PAM4 standards mandate FEC', which would need every such standard read. | — |
| C-12a | MIPI M-PHY v5.0 defines HS-GEAR5. | `interfaces/ufs4` | MIPI press release, M-PHY v5.0 | `public-rate` | **verified** — Public fact from the standards body's own announcement. Verifies the existence of the gear and nothing about its electricals. | — |
| C-12b | M-PHY HS-GEAR5 runs at 23.32 Gb/s per lane. | `interfaces/ufs4` | MIPI press release, M-PHY v5.0 | `public-rate` | **scoped** — The page said 23.2 Gb/s; the announcement says 23.32. Neither figure is wrong for a different quantity — raw versus post-encoding differ — so the page now states the raw rate and names it as raw. The discrepancy is why this is split from C-12a. | — |
| C-12c | UFS 4.0 binds M-PHY HS-GEAR5. | `interfaces/ufs4` | JESD220E and the M-PHY revision it references | `normative` | **awaiting** — MIPI’s own announcement establishes that M-PHY v5.0 defines HS-GEAR5 at 23.32 Gbps (recorded separately as C-12a). What needs JESD220E is the BINDING — that UFS 4.0 requires that gear rather than merely permitting it. Note also that JEDEC published UFS 5.0 (JESD220H) in February 2026 on M-PHY 6.0 with HS-G6, so the page should say which generation it describes. | — |
| C-13 | UFS over M-PHY uses spread-spectrum clocking. | `interfaces/ufs4` | MIPI M-PHY | `normative` | **awaiting** — Spread-spectrum clocking is described in M-PHY material as an option for EMI control, and the page should say optional rather than used. What needs the specification is whether UFS mandates it and with what modulation limits. | — |
| C-14 | An M-PHY burst requires re-acquisition from a preamble. | `interfaces/ufs4` | Mixel, "M-PHY benefits and challenges"; Synopsys M-PHY article, on HS-BURST structure and STALL | `commercial` | **scoped** — Confirmed by the burst structure: an HS-BURST is PREPARE, SYNC, MARKERs and then data, where SYNC is the symbol sequence the receiver uses to bit-synchronise to the embedded clock. Between bursts the lane sits in STALL with activity stopped, so each burst re-acquires. That is the mechanism the page describes. | — |
| C-15 | USB 3.2 spread-spectrum clocking is down-spread, 0 to -5000 ppm, at roughly 30 to 33 kHz. | `interfaces/usb-3x` | TI application note SDAA423, USB 3.1 Gen 1 host TX electrical compliance, SSC parameters | `commercial` | **scoped** — Independent sources agree on triangular down-spread modulation at 30 to 33 kHz. The depth is specified as a RANGE of 0.4% to 0.5%, so "0 to -5000 ppm" describes the maximum excursion rather than the required one, and the page says so. USB 3.2 clause 6.5.3 is named as the normative source and has not been read. | — |
| C-16a | USB 3.2 Gen 1 operates at 5 Gb/s. | `interfaces/usb-3x` | USB-IF, usb.org/usb-32-0 | `public-rate` | **verified** — Public rate fact from the standards body. Says nothing about electrical requirements. | — |
| C-16b | USB 3.2 Gen 2 operates at 10 Gb/s. | `interfaces/usb-3x` | USB-IF, usb.org/usb-32-0 | `public-rate` | **verified** — Public rate fact from the standards body. | — |
| C-16c | USB 3.2 Gen 2x2 operates at 20 Gb/s. | `interfaces/usb-3x` | USB-IF, usb.org/usb-32-0 | `public-rate` | **verified** — Public rate fact from the standards body. Two lanes, which is why it is split from Gen 2. | — |
| C-17 | Controlled impedance is typically specified to +/-10%, with +/-7% available at a premium. | `package-board/manufacturing-tolerance` | fabricator capability statements, not a standard | `commercial` | **scoped** — Presented as typical fabricator capability rather than a specification. | — |
| C-19 | The DC bias dependence of the same nominal MLCC part differs markedly between vendors, and X7R is not reliably less bias-sensitive than X5R. | `power-integrity/real-capacitors` | I. Novak, B. Williams, J. R. Miller, G. J. Blando, N. Shannon, 'DC and AC Bias Dependence of MLCC Capacitors and its Temperature Dependence', DesignCon East 2011 | `measured` | **verified** — Read from the paper's own conclusions, not from its plotted curves. The authors anonymise the vendors, which is why this site names no part's derating curve. This claim is the reason the panel takes the retained fraction as an input. Retrieved 12 September 2026 from the authors' paper archive. The link is http, not https: the https endpoint on that host returns 404, so an upgraded URL silently fails. | — |
| C-20 | MLCC DC bias sensitivity does not depend on temperature, so bias and temperature derating multiply as separable factors. | `power-integrity/real-capacitors` | Novak et al., DesignCon East 2011, conclusions | `measured` | **verified** — This is what lets docs/real-capacitor-model.md carry bias and temperature in one retained scalar rather than a two-dimensional surface. Recorded because it is a measured finding being used as a modelling licence. Retrieved 12 September 2026 from the authors' paper archive. The link is http, not https: the https endpoint on that host returns 404, so an upgraded URL silently fails. | — |
| C-21 | Beyond the immediate capacitance change when DC bias is applied, MLCCs show a slower settling that can move capacitance by as much as a further 25% over a few minutes. | `power-integrity/real-capacitors` | Novak et al., DesignCon East 2011, conclusions | `measured` | **verified** — Quoted on the page as a reason the retained fraction is a band rather than a number. The figure is the paper's stated bound, not one read off a curve. Retrieved 12 September 2026 from the authors' paper archive. The link is http, not https: the https endpoint on that host returns 404, so an upgraded URL silently fails. | — |
| C-22 | A successive-approximation converter compares against its reference once per bit trial, so a reference that moves during a conversion weighs the early bits differently from the late ones. | `labs/adc-interference` | Analog Devices, "Voltage Reference Design for Precision Successive-Approximation ADCs" | `commercial` | **verified** — States the mechanism directly: the reference is disturbed when the DAC inputs change, the DAC changes on each bit-test clock cycle, and the largest droop is at the MSB trial because that capacitor is the largest. That is exactly what this lab models. It describes charge-redistribution SAR parts; the lab’s trial TIMING within the sample period is a modelling choice and the page says so. | — |
| C-23 | A one-bit delta-sigma modulator's feedback DAC is scaled by the reference, so reference ripple multiplies the bitstream rather than adding to the signal. | `labs/adc-interference` | Analog Devices sigma-delta ADC tutorial and AN-0979, on the one-bit feedback DAC and its reference | `commercial` | **scoped** — The one-bit feedback DAC switching between levels set by the reference is standard in the published descriptions of this topology, which is what makes reference ripple multiply the bitstream rather than add to the signal. Scoped rather than verified because the page now bounds the behaviour to the loop it simulates — discrete-time, second order, one bit — and says a continuous-time or multi-bit modulator will differ. | — |
| C-24 | Counting interference as noise, with the fundamental, DC and harmonics 2 to 6 excluded, is the usual convention for a converter dynamic test. | `labs/adc-interference` | Analog Devices MT-003 tutorial, "Understand SINAD, ENOB, SNR, THD, THD+N and SFDR" | `commercial` | **scoped** — MT-003 defines SNR as the signal against all other spectral components below Nyquist EXCLUDING harmonics and DC, and SINAD as including harmonics but excluding DC. That is the convention this lab declares. The specific choices — harmonics 2 to 6, plus or minus 4 bins, Blackman-Harris — are this lab’s parameters, published in its result contract, not a standard’s requirement. IEEE Std 1241 has not been read and the page makes no compliance claim. | — |
| C-25 | Input-referred coupling appears as an offset error, a constant reference error as a gain error, and a reference that changes during the bit trials as a linearity error. | `labs/adc-interference` | Derived on this page from the converter model, and measured with it: offset 0.90 mV, gain −0.318 dBFS implying a 2.41 V effective reference, and THD rising to −53.5 dB | `measured` | **scoped** — Narrowed in this batch: DNL and INL are named as the mechanism and explicitly not measured, because the lab runs no static ramp or histogram test and THD is not a substitute for one. The resemblance to a static nonlinearity holds only while the disturbance repeats in step with the conversions, which the page now says. | — |
| C-26 | A sinc-cubed decimator is the usual filter after a second-order modulator, and it nulls exactly at multiples of the output data rate. | `labs/adc-interference` | Analog Devices AN-0979, "Digital Filtering Options", and the sigma-delta ADC tutorial | `commercial` | **verified** — Better than "the usual choice": there is a stated design rule. The sinc order should be at least one more than the modulator order to keep out-of-band noise from aliasing back, which puts a second-order modulator at sinc-cubed, and the notch position follows the output data rate directly. Both halves of the claim, from the manufacturer’s own filter documentation. | — |