SIPI

SI in practice / 09

Receiver Sampling, Clock Recovery, and Jitter Tolerance

By Geetansh Arora — Principal SI/PI Engineer11 min

Everything else on this site describes what happens to a signal on its way to the receiver. This page is about what the receiver then does with it — because on a modern link that is where most of the margin is created, and it is why an eye measured at the pad can be closed while the link runs perfectly.

Every preceding analysis in signal integrity focuses on the physical journey: how PCB transmission lines, vias, dielectric dissipation, and crosstalk distort a pulse train before it reaches the far end of the channel. However, a degraded waveform does not interpret itself. At the end of the channel sits a silicon receiver, tasked with converting noisy, dispersed, multi-gigahertz analog voltages back into pristine digital bits.

At its core, the receiver must execute two continuous, interrelated operations: when to look (establishing the optimal sampling phase in time) and what it saw (comparing the sampled voltage against a decision threshold). In legacy parallel buses like DDR memory, a companion clock trace travels alongside the data lines to dictate sampling instants. But at multi-gigabit SerDes speeds (10 to 112 Gbps), routing a separate physical clock trace is physically impossible: picoseconds of trace length mismatch, package delay differences, and thermal gradients would completely consume the timing window.

Instead, modern serial interconnects embed the clock directly within the data transitions. The receiver's Clock and Data Recovery (CDR) circuit acts as a specialized phase-tracking filter: it extracts a synchronous clock reference from the incoming data stream, tracks low-frequency wander, and positions the internal sampling clock precisely in the center of the received eye. Meanwhile, high-speed voltage comparators (slicers) resolve the signal amplitude. Understanding how the CDR loop, slicers, and AC coupling networks interact is where signal integrity meets digital silicon.

Two decisions, made continuously

A receiver is doing two things at once, forever:

Both decisions can be wrong, and they fail differently: a wrong instant is a timing failure, a wrong threshold is a voltage failure. The eye diagram's two axes are exactly these two questions.

Sampling phase: the receiver chooses it

The best sampling instant is not the middle of the symbol, and it is not the peak of the pulse response. It is the point that maximises the eye — which is a trade between pre-cursor and post-cursor interference, and it moves as the channel changes.

What a CDR converges on is its phase detector's balance point, which is not the same thing. A bang-bang (Alexander) detector equalises the number of early and late transition votes, which lands near the mean zero crossing — close to the widest opening on a symmetric eye, and measurably off it on an asymmetric one. A baud-rate detector such as Mueller-Müller drives a particular combination of the sampled levels to zero, which on a channel with strong post-cursor settles later than the widest opening. Neither searches for maximum margin; both happen to be near it when the eye is well behaved. So "the CDR finds the best phase" is a useful first approximation and a bad assumption when the eye is skewed — which is exactly when you are debugging.

A clock-and-data-recovery loop converges on it. Which means a fixed-phase measurement understates what the receiver achieves, and two eyes measured with different recovery settings are not comparable.

The CDR is a filter on jitter

This is the part most worth understanding, because it decides which jitter even reaches the decision.

The loop tracks the incoming data's timing. Jitter slower than the loop can follow is tracked out — the sampling instant moves with it, so the receiver never sees it. Jitter faster than the loop can follow passes straight through.

H(f) low-pass  ·  residual = 1 − H(f)  ·  tolerance = margin ⁄ |1 − H(f)| three functions, not two — and the third is one over the second, which is why it rises where the second falls

That deserves spelling out, because naming the wrong one of the three is the commonest confusion in this subject — and an earlier version of this page made exactly that mistake.

Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.

One loop · three readings analytical peak transfer — residual −3 dB — worst tolerance — —
Jitter transfer
Input jitter onto the recovered clock. Low-pass: the loop follows slow wander.
Residual phase error
What is left at the decision — the complex complement 1 − H(f). High-pass.
Jitter tolerance
The jitter the receiver withstands: margin ⁄ |1 − H|, and a declared ceiling where a real phase detector runs out of range.
Clock phase in time
Steady-state sinusoidal experiment: input phase (dashed), recovered clock (blue), and their residual (amber), aligned in time. This shows small-signal response after settling, not lock acquisition.

Two consequences that cause real confusion:

Adaptation, and its limits

A modern receiver adapts: it adjusts its CTLE boost and DFE taps until some internal metric is optimised. Three things about that are worth knowing.

It needs time and transitions. Adaptation converges over thousands of symbols, so the first part of any capture is the receiver settling, not a result. On a burst-mode link that re-converges every wake, this is the dominant design problem — see UFS.

It has a range, and running out of it is the real signal. Coefficients sitting at their limits mean the channel is outside what the reference equaliser was defined against. That is far more informative than an eye photograph, and it is available from the link itself.

It optimises its own metric, not yours. A receiver converging to maximum eye height may accept more jitter to get it. What it converged to is a fact about the receiver as much as about the channel.

AC coupling and baseline wander

Many serial interfaces are AC-coupled, with series capacitors in each line, so the two ends need not agree on a common-mode voltage — PCIe and USB 3.x place them in the lane, and where they sit and what value they take is specified per interface rather than assumed. It is not universal: plenty of short-reach and chip-to-chip links are DC-coupled and negotiate a shared common mode instead, and the parallel memory interfaces on this site have no series capacitor anywhere. Where the capacitors are present the cost is that DC content cannot pass.

A long run of identical bits has DC content. With it blocked, the signal droops towards the coupling capacitor's mid-point during the run and jumps when it ends — baseline wander. The decision threshold is then in the wrong place for the bits at the end of the run, which is exactly where the margin was already thinnest.

droop over a run ≈ trun / (RC) so the defence is a long RC and a bounded run length — and the encoding is what bounds the run

This is why line coding exists — though the three common answers do different jobs and only two of them give a guarantee. 8b/10b is a constrained code: the mapping table itself excludes long runs, so a bounded run length and a bounded disparity are properties of the code no payload can defeat. 128b/130b with scrambling is not. Scrambling XORs the payload with a known pseudo-random sequence, which makes long runs overwhelmingly unlikely for ordinary data and improves the average transition density — but a payload that happens to match the scrambler's output produces exactly the run the scrambler was supposed to break up. It is a statistical improvement, not a bound, and standards that rely on it add a sync header and a periodic scrambler reset rather than claiming otherwise. The distinction matters when you are choosing a test pattern: a compliance pattern is chosen to defeat the statistics on purpose.

Using this to find a fault
  • Errors at the end of long runs. Baseline wander. Check the coupling capacitor value and the coding's run-length bound before looking at the channel.
  • Errors only in the first microseconds after a link comes up. Adaptation has not converged. Normal on a burst-mode link, a defect on a continuous one.
  • Adapted coefficients pinned at a limit. The channel is outside the reference equaliser's design range. This is a budgeting problem, not a tuning one.
  • Jitter numbers that disagree between two instruments. Compare the CDR loop bandwidths before suspecting anything physical.
  • A closed eye at the pad on a link that works. Expected on a modern serial standard. Measure after the equaliser, or read the adapted settings instead.
Go deeper — why tolerance and transfer are opposite, and what a slicer really compares

Transfer, residual and tolerance are three readings of one loop. Jitter transfer H(f) asks how much of the input jitter appears on the recovered clock: the loop follows slow input jitter, so transfer is low-pass. The residual phase error at the decision carries the complex complement 1 − H(f), which is high-pass — whatever the loop tracked is no longer a timing error. And the input jitter the receiver can tolerate is its sampling margin divided by that residual factor, which is large at low frequency because the divisor is small there.

This page previously said tolerance is high-pass and rises steeply at low frequency, which cannot both be true: a high-pass response falls at low frequency. The sentence was reaching for a real fact and naming the wrong function. Tolerance is not high-pass; it is one over a high-pass, and that is exactly why it rises.

For a second-order type-2 loop, which is what the panel above models:

H(s) = (2ζωns + ωn²) ⁄ (s² + 2ζωns + ωn²) far above ωn, |1 − H| → 1 and tolerance → the bare sampling margin; far below, |1 − H| → (f/fn)² and tolerance rises as 1/f²

Two things fall out of that form which a first-order sketch cannot show. A type-2 loop peaks above unity even when it is nominally well damped — at ζ = 0.7 the panel reports about +2.1 dB — because the numerator's zero lifts the response near ωn. That is why jitter transfer is specified separately from loop bandwidth: a loop can amplify jitter in a band while still being called a 4 MHz loop. And the 1/f² rise in tolerance does not continue for ever. A real phase detector has finite range and a real VCO has finite tuning, so past some amplitude the loop loses lock however slowly the jitter moves. The panel draws that ceiling as a dashed line and labels it declared, because it is an assumption rather than a result.

Jitter Transfer (JTF) vs. Jitter Tolerance (JTOL). The CDR loop governs receiver timing through two complementary transfer functions:

  • Jitter Transfer Function (JTF, H(s)): Describes how much input jitter on the incoming data appears on the recovered clock. A CDR is a low-pass filter for jitter: phase modulations slower than the loop bandwidth (f < fLBW) pass directly onto the recovered clock with unity gain (0 dB). Jitter faster than fLBW is filtered out, leaving the recovered clock clean and quiet.
  • Jitter Error Function (He(s) = 1 - H(s)): The relative timing error between the incoming data and the recovered clock — the exact jitter that closes the eye at the slicer latch. Because H(s) ≈ 1 at low frequencies, the error function exhibits a steep high-pass response: low-frequency jitter produces near-zero phase error because the clock tracks the data perfectly.
  • Jitter Tolerance (JTOL, 1 / |He(s)|): The amplitude of sinusoidal jitter the receiver can tolerate before dropping bits. At low frequencies, JTOL climbs at 20 dB/decade (or 40 dB/decade for second-order loops), allowing the receiver to effortlessly tolerate tens or hundreds of Unit Intervals (UI) of low-frequency wander (such as Spread-Spectrum Clocking, SSC). Above fLBW, tolerance flattens to an asymptotic high-frequency floor (typically 0.15 to 0.25 UI), strictly bounded by the receiver's intrinsic setup/hold aperture and internal thermal noise.

AC coupling and baseline wander. High-speed serial links almost universally place series AC coupling capacitors (typically 100 nF in 0201 or 0402 packages) in the signal path. These capacitors isolate the DC bias of the transmitter's output stage from the receiver's internal common-mode termination (Vcm), preventing DC ground loops and enabling interoperability between different semiconductor process nodes.

However, the capacitor interacts with the channel's termination resistance (50 Ω single-ended, 100 Ω differential) to form a high-pass filter with a low-frequency cut-off: fc = 1 / (2 π · Rterm · C). While this cut-off is typically low (a few tens of kilohertz), it cannot pass true DC. If the transmitted data contains a long run of Consecutive Identical Digits (CID) — such as dozens of consecutive ones — the coupling capacitor slowly charges toward the supply voltage. When the data eventually transitions back to a zero, the average DC baseline has drifted upward.

This phenomenon — baseline wander — shifts the vertical center of the waveform relative to the slicer's fixed reference threshold, directly eroding vertical eye height and triggering false bit flips. To prevent baseline wander from destroying margin, high-speed protocol architectures rely on two defenses: DC-balanced block encoding (such as 8b/10b, 64b/66b, or 128b/130b) and digital PRBS scramblers that guarantee high transition density and strictly bound the maximum allowable run length of identical bits.

What this model is not. A compliance jitter-tolerance mask carries more than a loop: a BER target, a defined test pattern, the phase detector's own characteristic, and usually a measured rather than modelled low-frequency corner. Transfer and tolerance are also not independent specifications — a loop bandwidth chosen to improve one necessarily moves the other. A wider loop tracks more jitter out, so tolerance improves over a wider band, and it passes proportionally more of its own reference's noise onto the recovered clock.

What a slicer compares against. The threshold is not a fixed voltage. It is derived from the receiver's own supply and reference, which is precisely why rail noise becomes timing noise: move the reference and every input moves relative to it, including the quiet ones.

For PAM4 there are three thresholds, and they have to be placed accurately relative to levels that are not perfectly evenly spaced. That is why a PAM4 link reports three eye heights, and why one eye being worse than the others points at the device rather than the channel.

And a note on what the receiver does to error statistics. A DFE that makes a wrong decision feeds a wrong correction into the next few bits, so errors arrive in bursts rather than singly. That matters enormously to a forward-error-correction budget, which is designed around burst-correcting capacity. The receiver is therefore part of the error model, not just a consumer of the signal.

The burst is not bounded by the tap count, and that is worth being precise about. A single wrong decision corrupts the corrections applied to the next N bits, where N is the tap span — but any one of those corrupted bits can itself be decided wrongly, and then it seeds a fresh N-bit window. The feedback is recursive, so the burst length is not N; it is however long the chain of induced errors happens to run. On a healthy channel it usually terminates within a tap span or two, because each induced error needs the residual margin to be small as well. On a marginal one it can run much longer, and the distribution has a tail that a "bursts are N bits" model does not contain. This is the mechanism behind the difference between a DFE's ideal and decision-directed modes, which the impairment panel exposes as a toggle — ideal cancellation knows the transmitted bits and cannot make this mistake at all.

In the real world

The practical shift this page describes is that analogue eye measurements have become much less informative than they used to be. A specification that assumes a reference receiver with a defined CTLE, DFE and CDR is permitting channels that would have been unusable a generation earlier — and permitting the eye at the pad to be completely closed.

So the questions worth asking a link are no longer "what does the eye look like?" but what did the equaliser converge to, how much range was left, and at what loop bandwidth was the jitter measured? All three come from the link itself, and all three say more than a photograph.

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