Power Delivery Networks: From Regulator to Die

Start with what the chip is actually doing

On a schematic or a bench multimeter, power distribution looks deceptively simple: a voltage regulator produces 0.85 V, a copper plane carries it across the board, and the chip receives power. If the multimeter reads 0.850 V, it is tempting to assume the job is done. But a multimeter only measures at zero hertz. To the switching transistors inside a modern die, the power delivery network (PDN) is not a static rail — it is a high-speed electrical supply chain tasked with delivering precise packets of charge on picosecond timescales.

An ideal PDN would behave like a zero-impedance battery at every conceivable frequency: whether the load draws zero amps or fifty amps, steady-state DC or sub-nanosecond pulses, the rail voltage would not move by a microvolt. In the physical world, every conductor between the regulator and the logic gates — traces, vias, planes, BGA balls, package substrates, and on-die metal layers — has inductance. That inductance turns the apparent “wire” into a frequency-dependent impedance ladder, where drawing sudden current inevitably forces the supply voltage to move.

Inside a digital chip, almost all the current is drawn in bursts. A clock edge arrives, millions of gates switch at once, each one charging or discharging a tiny capacitance, and for a few tens of picoseconds the chip pulls a great deal of current. Then it goes quiet until the next edge.

So the load is not a resistor. It is closer to a square wave of current, with a small average and a very large rate of change — the di/dt that causes all the trouble. A core that averages 8 A might swing several amps within a nanosecond when a clock gate opens.

Now ask where that current comes from. The regulator is centimetres away, and the connection to it has inductance. Inductance opposes a change in current — that is its definition. So the regulator physically cannot supply a nanosecond-scale burst; by the time it responds, the event is long over.

Everything in power integrity follows from that one problem: the load needs current faster than the source can deliver it, so something closer has to hold a local reserve. Every capacitor in the PDN exists for that reason, and the only question is how close and how fast.

One law, applied at every frequency

A digital circuit does not draw DC. It draws a current that steps, rings and repeats — a broadband waveform with energy from kilohertz to gigahertz. Ohm's law still applies at every one of those frequencies, so the voltage wobble on the rail is simply V_noise(f) = I_transient(f) × Z_PDN(f). Everything in power integrity is an attempt to keep that product inside a budget.

What makes it hard is that Z_PDN is not one number. It is a curve across eight decades of frequency, and it is built out of physically separate hardware that hands off from one stage to the next.

The chain, and who owns what

Stage	Roughly owns	Limited by
VRM control loop	DC – ~100 kHz	feedback loop bandwidth
Bulk capacitors	~100 kHz – ~1 MHz	ESR, then ESL
Board ceramics	~1 – 100 MHz	mounting inductance
Package caps + planes	~100 MHz – several hundred MHz	package inductance
On-die capacitance	above that	silicon area

Read that table as a set of ceilings rather than a set of assignments. Each stage stops working where its own series inductance takes over, and past that point the next stage down is on its own. This is the single most consequential fact in PI, and it has a blunt corollary: nothing you add on the board can help above a few hundred megahertz, because the inductance of the balls, vias and package planes between the board and the die isolates the two.

Why does this hierarchy exist in exactly this order? It is an unavoidable trade-off between energy storage and loop inductance dictated by physical distance. A power supply chain works like a bucket brigade:

The VRM and bulk capacitors sit centimetres away. They can store massive amounts of energy (hundreds of microfarads to millifarads), but their current must travel across long traces, through plane spreading resistance, and around large geometric loops. That path has tens of nanohenries of inductance. By V = L·di/dt, trying to draw nanosecond current bursts through that loop causes an immediate voltage collapse. The VRM feedback loop simply cannot react faster than tens of kilohertz to a few hundred kilohertz.
Board ceramic capacitors (MLCCs) sit millimetres from the chip. Their capacitance is smaller (100 nF to 10 µF), but their mounting loops can achieve an inductance around 1 to 2 nH. They supply charge during the tens-to-hundreds-of-nanoseconds window while the bulk caps and VRM are still ramping up.
The package (planes and land-side/die-side capacitors) sits inside the BGA boundary. The solder balls and vias connecting the board to the package form an inductive fence of roughly 100 to 300 pH. Above ~100 MHz, this fence isolates the board. Inside the package, thin dielectrics and tiny geometries drop loop inductance below 50 to 100 pH, maintaining low impedance up to several hundred megahertz.
On-die capacitance sits microns from the transistors. Real estate on silicon is the most expensive conductor on the bill of materials, so on-die capacitance is limited to tens or hundreds of nanofarads (from thin gate oxides and dense metal-fill structures). But its loop inductance is measured in single-digit picohenries. It is the only reservoir fast enough to feed sub-nanosecond switching bursts in the gigahertz regime.

Each tier’s sole responsibility is to supply charge long enough for the next slower, larger tier further out to take over. When that handoff fails — or when the capacitance of one tier rings against the inductance of the tier behind it — the rail develops an impedance peak.

The most common wasted afternoon A first-droop problem — nanosecond timescale, hundreds of megahertz — cannot be fixed by adding board capacitors, no matter how many or how close. The current has to come from on-die or in-package capacitance, because those are the only sources inside the inductive fence. Confirm which droop you have before you touch the BOM.

The flip side is that the handoffs are where the trouble lives. Where one stage runs out of capacitance and the next has not taken over, the network looks inductive against something capacitive, and the impedance curve grows a peak. Those peaks are structural — they come from package and board geometry, not from a component you chose — and they are the reason the PDN gets analysed as a whole rather than stage by stage.

Why this decides how your board behaves

The rail moving is not, in itself, the failure. What it does downstream is:

Timing moves. A gate's delay depends on its supply voltage. Drop the rail and every path gets slower — which shows up as jitter at the outputs, not as a power problem. This is the single most under-diagnosed cause of jitter on a link. See PDN-induced jitter.
Noise margin shrinks. A receiver's threshold is referenced to its own supply. Rail noise eats directly into the voltage margin your channel budget assumed.
Analogue blocks degrade first. A PLL or a SerDes front end has a finite power-supply rejection ratio, and what gets through becomes phase noise.
Emissions. A PDN with a resonance is a structure that rings, and a ringing plane pair radiates. See plane resonance.

What to do about it

First, work out which band your problem is in. This is the whole game, and almost every wasted effort in PI comes from skipping it. A microsecond-scale droop is a VRM or bulk-capacitor problem. A nanosecond-scale one is a package or die problem, and no board component can reach it. Measure the timescale before you touch the BOM.

Then fix the thing that owns that band. The table above is a map of who can help. Adding board ceramics to fix a 300 MHz droop is the classic wasted afternoon; the inductance of the balls and vias between the board and the die isolates the two completely.

Treat the peaks as structural, not as component choices. The handoffs between stages are where impedance peaks live, and they come from package and board geometry rather than from a part number. Moving them usually means changing inductance, not capacitance.

Compare the impedance against the load's spectrum, not against a flat line. A peak where the load has no energy costs nothing. A smaller peak sitting on a clock harmonic dominates. See target impedance for why the single-number version of this is both useful and a simplification.

Using this to find a fault

Measure the droop's duration first. It names the responsible stage more reliably than anything else. Microseconds is the VRM loop; hundreds of nanoseconds is bulk; tens of nanoseconds is board ceramics; nanoseconds is package; sub-nanosecond is on-die and you cannot reach it from outside.
Ringing after a load step. Read its frequency. That is an anti-resonance, and the two stages fighting at it are the two whose handoff sits there. See anti-resonance.
Noise that appears on a rail nothing on that rail explains. Check what else shares the plane. Transfer impedance means a noisy block can disturb a quiet one without any DC connection between them being at fault.
A problem that moves when you probe it. A scope probe's ground lead is an inductor and its tip is a capacitor. On a PDN measurement that is not a small perturbation — use a proper low-inductance connection before believing the waveform.

Go deeper — why inductance sets every ceiling, and what a single impedance number hides

Every ceiling in the table above is an inductance. It is worth seeing why in one line. A capacitor is only a capacitor below its self-resonant frequency:

f_SRF = 1 / ( 2π √( L · C ) ) above it, |Z| = wL and the capacitance is irrelevant — the part is an inductor with a part number

The L in that expression is not mostly the capacitor. It is the mounting inductance: the pads, the vias, and the loop the current takes from the plane to the part and back. That is geometry, not a purchasing decision, and it is why moving a capacitor two millimetres can matter more than doubling its value — and why the same part behaves differently on two boards.

The same argument applies one level up. The package's balls and vias present an inductance between the board's capacitors and the die. Above the frequency where that inductance dominates, the board is simply not connected to the die in any useful sense. That is the "inductive fence", and it is the reason on-die capacitance exists at all despite costing silicon area.

What a single impedance number hides. The product V = I × Z is exact at every frequency, but collapsing it into one target impedance assumes the load draws current at every frequency equally. No real load does. A processor's current spectrum has structure — clock harmonics, workload-dependent envelopes, power-state transitions — and the honest question is whether Z is low where I is large. The PDN lab plots the current spectrum on its own axis next to the impedance for exactly this reason.

One more thing the single number hides: transfer impedance. |Z| at the die answers "how much does the rail move when this block draws current?" It does not answer "how much does a noisy block over there disturb me?" That is a different quantity, and on a shared plane it can be the one that matters.

In the real world

Power integrity is mostly an argument about ownership. The die's capacitance is the silicon team's, the package's is the package team's, the board's is yours, and the current profile that drives all of it belongs to whoever wrote the firmware. Problems surface at the handoffs — both the electrical ones and the organisational ones, which tend to be in the same places.

Which is why the most valuable thing you can do early is get a model of the whole chain rather than of your part of it. A board-only PDN simulation is not wrong so much as unable to answer the question, because the peak that will hurt you is almost always at a boundary between two pieces that different people own. See Lab C, which puts the whole ladder on one page, compares die and board load timing, and says in amps which stage is supplying the load at every frequency.