PDN Anti-Resonance and Impedance Peaks

A parallel LC is a maximum, not a minimum

Basic circuit intuition tells you that putting components in parallel reduces overall impedance: two identical resistors in parallel halve the resistance, and two identical capacitors in parallel halve the capacitive reactance. It seems logical that scattering capacitors of different values across a power rail should make the rail's impedance drop across every frequency band. Yet in high-speed power integrity, doing exactly that often produces the opposite result: a sharp, towering spike of high impedance right where you needed clean power most.

This apparent paradox is an anti-resonance. It occurs because real capacitors are not ideal. Every capacitor has parasitic series inductance (ESL and mounting loop inductance), which causes it to turn into an inductor above its self-resonant frequency. When you place a larger capacitor in parallel with a smaller one, there is inevitably a middle frequency where the larger part has already become an inductor while the smaller part is still behaving as a capacitor. You have inadvertently connected an inductor in parallel with a capacitor — forming a classic parallel LC tank circuit across your power rail.

Series resonance is the familiar one: an inductor and a capacitor in series, and at the frequency where their reactances cancel, the impedance collapses to whatever resistance is left. That is what makes a capacitor useful — its self-resonance is the point of lowest impedance.

Put the same two elements in parallel and the arithmetic inverts. Their reactances still cancel, but now they are cancelling in the denominator, and the parallel combination goes to a maximum. At that frequency the pair looks like a large resistance, and current circulates between them rather than flowing to the load.

That is the entire mechanism, and everything below is a consequence of noticing where such pairs occur. They occur wherever one part of the network has passed its own resonance and turned inductive while the next part is still capacitive — which is to say, at a handoff between two stages of a PDN. Not every handoff produces a visible peak: if the two stages resonate close together, or if there is enough series resistance in the loop between them, the pair is damped and the curve simply passes through. What is reliable is the converse — a peak between two stages is such a pair, so a peak tells you where to look.

How a peak appears from two good parts

Take a 10 µF bulk part and a 100 nF ceramic. Below both self-resonant frequencies they are both capacitors and they add — fine. Above both, they are both inductors in parallel — also fine, the inductance halves. The trouble is the band in between: the 10 µF is past its SRF and behaving as an inductor, while the 100 nF has not reached its SRF and is still a capacitor.

An inductor in parallel with a capacitor is a tank circuit, and at its resonance the parallel combination goes to a maximum, not a minimum. The peak's height is set by how lossy the loop is:

Q = (1 / R) √( L / C ) R here is the total series resistance in the loop — mostly the two capacitors' ESR. Halve the resistance and the peak doubles. This is why a bank of very low-ESR parts can measure worse than a mixed one.

Check the complete curve after changing a capacitor bank A value added to lower one region can introduce anti-resonances with neighbouring stages and raise another region. Adding more of an existing value avoids a new nominal C value, but it also changes bank ESR, ESL, and interaction with shared mounting paths. Recompute the mounted network after either change.

Structural peaks need structural context

Component-to-component anti-resonance is the textbook case. Other peaks come from boundaries between board, package, and die, so a board BOM change may have limited influence on their frequency or damping:

Board caps against package inductance, typically in the tens of megahertz. The board's capacitance looks inductive through the balls and vias, resonating against the package's own capacitance.
Package against die. Package inductance against on-die capacitance, usually in the low hundreds of megahertz. This is the first-droop resonance, and it is the one that shows up as periodic jitter.

For those, the levers are different in kind: add damping rather than capacitance, move the resonance by changing the package's inductance or the die's capacitance, or — most often in practice — compare the peak with a bounded load-current spectrum. A peak with negligible excitation may be acceptable, but document the workload evidence and margin rather than assuming that an unmeasured spectral gap is quiet.

Why this decides how your board behaves

Peaks are where the rail actually moves. A PDN's noise is I × Z, so the frequency where Z is largest is where a given current does the most damage. The peak, not the average, is the design constraint.
Adding capacitance can move rather than remove a peak. A new value creates another interaction, while more identical parts change the bank's effective ESR and ESL. Evaluate the resulting network rather than inferring improvement from capacitance alone.
Lower ESR can make it worse. ESR is the damping. A bank of very low-loss parts has a taller peak than a mixed one, which inverts the usual instinct that a better capacitor is better.
A peak only costs you if the load excites it. This is the redeeming feature and the reason the impedance curve alone is not a verdict. Compare it with the current spectrum before spending anything.

Model the mounted population and its spread Use bias- and temperature-adjusted capacitance, representative ESR and ESL, mounting-loop inductance, and component tolerance. Sweep those quantities or measured populations: a nominal curve can place a narrow peak between activity lines while production variation moves it onto one. Correlate the model with impedance or load-step measurements at the same reference point.

What to do about it

Damp it rather than trying to remove it. The peak's height is set by Q, and Q is set by resistance. Deliberately choosing a part with higher ESR — or adding a small series resistance — flattens the peak at the cost of slightly raising the floor. Controlled-ESR capacitors exist for exactly this, and choosing a "worse" capacitor on purpose is a legitimate and underused move.

Move it, if you cannot damp it. The resonant frequency is set by the L of one stage and the C of the next. Changing either moves the peak — so if there is a band where the load has little energy, move the peak there rather than trying to eliminate it.

Reduce the inductance that created it. Lower L lowers both the peak frequency and √(L/C), which is the peak's height scale. This is the only lever that improves both at once, and it is a layout and stackup change rather than a BOM one.

Resist the instinct to fill gaps with new values. The classic failure is seeing a rise in the curve, adding a value chosen to cover it, and finding the curve got worse — because the new part brought two new anti-resonances with it and one of them landed in the gap.

Using this to find a fault

Ringing after a load step. Measure its frequency. That is the anti-resonance, and the two stages fighting at it are the two whose handoff sits there. In Lab C the topology panel names them directly.
A peak that moved when you changed a capacitor value. Expected — you changed the C in one half of the tank. If it moved into a worse place, that is information about where your load's energy is.
A peak that got taller when you added parts. Damping. Check the bank's total ESR before and after.
Two identical boards, different peak heights. Look at the mounting inductance and at the capacitors' actual capacitance under bias — both vary, and both move the tank.

Go deeper — peak Q and the main damping levers

At the parallel resonance the impedance magnitude is approximately Q times the characteristic impedance of the tank:

|Z|_peak ≈ Q · √( L / C ) Q = (1/R) √( L / C ) so |Z|_peak ≈ L / (R·C) — and every lever you have is one of those three symbols

Writing it as L/(RC) makes the whole design space visible at once. There are exactly three things you can do to a peak, and the expression says what each one costs:

Raise R — damping. Lowers the peak proportionally, raises the floor slightly in the band where that bank is doing its job. Cheap, and the usual answer.
Raise C — lowers the peak and moves it down in frequency. Two effects, and the second is why "add capacitance" sometimes helps and sometimes relocates the problem onto something else.
Lower L — lowers the peak and moves it up. The only lever that improves the height without a frequency trade you might regret, and the hardest to change, because it is geometry.

Practical mitigation: value spacing and ESR damping. Understanding the tank reveals why two ubiquitous design practices either succeed or fail catastrophically:

The decade-spacing trap: A historical rule of thumb recommended staggering decoupling values by decades — placing a 10 µF, a 1 µF, a 100 nF, and a 10 nF capacitor on every rail. Because each value is separated by a 10× ratio, their self-resonant frequencies are separated by roughly a factor of 3. In low-loss ceramic networks, this creates three distinct, sharp anti-resonant peaks between the dips. Modern high-density designs often achieve a flatter impedance profile by populating multiple copies of a single well-mounted value (such as 1 µF or 100 nF), or by restricting value steps to no more than a factor of 2 or 3 to keep anti-resonant peaks shallow and damped.
Targeting critical ESR damping: For a parallel LC tank formed by inductance L and capacitance C, the characteristic tank impedance is Z_tank = √(L / C). If the branch ESR satisfies R ≈ √(L / C), the tank is critically damped (Q ≈ 1), and the anti-resonant peak collapses completely into a smooth transitional plateau. Replacing high-ESR electrolytic or tantalum capacitors with ultra-low-ESR MLCCs without compensating for this loss is the single most common reason a revised PCB suddenly fails radiated emissions or transient ripple tests.

The peaks you cannot buy your way out of. Component-to-component anti-resonance is the textbook case and the easiest to fix. The structural ones are harder: the package's inductance against the on-die capacitance sets a peak whose frequency is fixed by the package design, and no board component is inside that loop. Similarly, the plane pair itself has resonances — see plane resonance — which are set by board dimensions rather than by anything on the BOM.

One measurement caution. A peak measured at one port may not exist at another, because the currents circulating in a tank are local. This is the multiport point again: damping a peak seen at the die may do very little for one seen at a bypass capacitor several centimetres away, and vice versa.

In the real world

Anti-resonance illustrates why adding capacitance does not always lower impedance at every frequency. Interactions among capacitance, inductance, and resistance can make an impedance peak grow even when each added component is useful on its own.

This is a practical reason to simulate the PDN as a network rather than specifying it only as a parts list. A BOM cannot show where the peaks are, while an impedance curve can reveal how a peak changes as parts are added.