High-Speed Vias: Stubs, Resonance, and Backdrilling

What a via actually is

A via is the vertical highway between layers of a PCB. You cannot route a signal from the top of a board to an inner layer without drilling a hole through the stackup and plating its walls with copper. That plated hole — the via barrel — is a short piece of transmission line, and in principle it works fine.

The problem is that a standard through-hole via is drilled through the entire board, whether the signal needs all of it or not. If your signal enters at layer 2 and exits at layer 4, the barrel keeps going for another eight layers below — connected at one end, open at the other, doing nothing useful. That leftover section is the stub, and it behaves as a resonant dead-end. At the frequency where the stub is a quarter-wavelength long, the wave that travels down it and back arrives exactly out of phase and cancels the signal at the junction. The result is a deep notch in your S₂₁ plot at a frequency you did not choose — and which can land right in the middle of your channel's operating band if the board is thick enough.

A plated through-hole is a copper tube — a barrel — drilled through the board, with a pad at each layer it connects to and an antipad, a clearance hole, cut into every plane it passes through so it does not short to them.

Electrically, those three features are an inductance, a capacitance, and a hole in the reference plane. The barrel is a conductor with a current loop around it, so it has inductance. The pads face the planes across the antipad gap, so they have capacitance. And the antipad is a gap in the plane that the signal's return current has to get around. None of those is on your schematic.

Whether that combination behaves as a transmission line of roughly the right impedance or as a lump of the wrong one depends on the ratio of its L to its C — the same √(L/C) as any other geometry. A via with a big pad and a tight antipad is capacitive and its impedance is low; a via with a small pad and a generous antipad is inductive and its impedance is high. Neither is automatically 50 Ω, and the discontinuity is the difference.

The stub is a resonator

Now the part that does the real damage on thick boards. A through-hole via is drilled through the whole board whether the signal needs it or not. If the signal enters at the top and leaves on an inner layer, the section of barrel below that exit layer is still there, connected at one end and open at the other.

That is a quarter-wave resonator, and it does something specific. At the frequency where the stub is a quarter wavelength long, a wave that travels down it and back comes home having taken half a wavelength — exactly out of phase — and cancels the signal at the junction. The open end has been transformed into a short circuit across your signal path. The result is a notch in S₂₁ that can be tens of decibels deep.

f_res [GHz] ≈ 2950 / ( L_stub[mil] · √D_k ) A 60 mil stub in D_k 4.0 resonates near 24 GHz. A 200 mil stub — a thick backplane, signal exiting near the top — lands at about 7.4 GHz, inside the frequency range that may matter to a 16 GT/s link.

The pattern that number reveals is the useful part: stub problems scale with board thickness. A thin board tends to push the first stub resonance upward, while a thick backplane can place it inside the channel band. Whether it matters depends on residual length, material, edge spectrum, and how strongly the junction excites the stub.

Why a deep notch is different from smooth loss A CTLE applies a smooth, gently rising gain across frequency. It has no mechanism to restore energy at one specific frequency where the channel has cancelled it — there is nothing left there to amplify without also raising noise. The practical remedies are to move the resonance outside the required band, reduce its excitation, or shorten the stub. See Lab B, where adding a stub puts a null in S₂₁ that a smooth equaliser cannot reconstruct.

Backdrilling, and what is left over

Backdrilling is a second, larger drill from the far side that removes the unused copper. It works well — but it cannot remove all of it, because drilling into the exit layer's pad would destroy the connection. A residual stub of roughly 5–10 mil is normal, plus the drill's depth tolerance. That residue pushes the resonance up by an order of magnitude, which is usually enough to get it out of band entirely.

The alternatives each cost something different. Blind and buried vias remove the stub by construction but add lamination cycles and cost. Choosing exit layers so signals leave near the bottom of the stack makes the leftover barrel short without any extra process. On a package substrate the whole question changes shape — the structures are thin enough that stub resonance is rarely the limit, and via inductance becomes the thing to worry about instead.

The rest of the via Even with no stub, a via is a discontinuity. The pad and antipad set its capacitance, the barrel sets its inductance, and the pair rarely land at the line's impedance. Enlarging the antipad reduces capacitance and raises the via's impedance — useful when the via is capacitive, harmful when it is not, and always at the cost of interrupting the plane the return current needs. As with most via problems, the fix is only as good as the return path you leave next to it.

Why this decides how your board behaves

A deep in-band notch can close the link. Unlike smooth loss, which consumes margin gradually, a resonance can strongly suppress a narrow part of the signal spectrum and create long-lived ISI.
The impedance bump costs reflections. Even a stubless via is a short section at the wrong impedance. One is negligible; a differential pair crossing a twenty-via connector field is not, because the reflections add coherently when the vias are evenly spaced.
The antipad costs return path. Every via perforates every plane it passes. In a dense BGA escape the antipads merge into what is effectively a slot, and the return current for every signal in that field has to find its way around it. See return current paths.
A layer change needs a return via. When the signal changes reference plane, its return must change too. Without a stitching via beside it, the return goes the long way and the loop inductance is whatever that detour happened to be.

What to do about it

Choose exit layers before you consider backdrilling. Routing a high-speed signal so it leaves near the bottom of a top-entry through via can minimise the unused barrel without adding a drilling operation. Confirm the remaining geometry and fabrication tolerance; this stackup and floorplan decision is easiest to make early.

Backdrill when the stub must exist. A second, larger drill from the far side removes the unused copper. Specify the residual you can live with, not the drill depth — the fab controls depth and you care about what is left. Then check the resonance of the residual, not of zero.

Provide the intended return transition beside the signal via. For reference planes on the same net, this is commonly a nearby stitching via. For different reference nets, use an appropriate low-inductance AC connection and verify the complete loop rather than adding a ground via that the return cannot use.

What a useful via model must include Define port and reference-plane locations, pad and antipad geometry on every traversed layer, the residual barrel, nearby return transitions, and the surrounding plane openings. For a differential pair, preserve pair orientation and mixed-mode port order. Compare both TDR and S-parameters; either view alone can hide where the discontinuity was introduced.

Tune the antipad only when you know which way the via is wrong. Enlarging the antipad reduces capacitance and raises the via's impedance — which helps a capacitive via and makes an inductive one worse, and always at the cost of interrupting the plane the return current needs. Measure first.

Using this to find a fault

A deep, narrow null in S₂₁. Read its frequency and invert the stub formula. If the length it implies matches a plausible leftover barrel, you have found it — and no receiver setting will help.
A link that fails on thick boards and passes on thin ones with the same schematic. A via stub is a strong candidate; compare residual barrel lengths and the corresponding notch frequencies before attributing the difference.
TDR shows a dip exactly at a via field. Capacitive — pads too large or antipads too tight. A bump instead means inductive, and usually means the return vias are missing or far away.
Backdrilled boards that still show a notch, at a higher frequency. Check the residual stub against the drill depth tolerance, not the nominal. The tolerance is what sets the worst case, and it varies lot to lot — which is exactly the pattern that looks like a mystery yield problem.

Go deeper — where 2950 comes from, and why a package via is a different problem

The constant is just unit conversion. A quarter-wave resonance happens when the stub length equals λ/4, and λ = v/f with v = c/√D_k:

f_res = c / ( 4 · L_stub · √D_k ) c in mil/s gives 2950 when f is in GHz and L in mil

Two refinements matter in practice. First, the effective D_k a via sees is not the laminate's bulk value — the field in the antipad region is partly in the resin-rich area around the barrel — so measured resonances usually land a little above the formula. Second, the notch has finite depth because the stub is lossy and because the junction is not ideal; a very short stub gives a shallow notch that reads as ripple rather than as a null.

The third feature, the antipad, deserves its own note because it is the one people tune last and should often tune first. Widening an antipad does three things at once: it lowers the via's capacitance (good, if the via is capacitive), it increases the loop area the return current must take around it (bad, always), and on a dense field it merges with its neighbours into a slot (very bad). The first effect is local and modelled; the second and third are global and usually are not.

On a package substrate the whole question changes shape. The structures are thin enough that stub resonance is rarely the limit — a 4 mil stub resonates well above 300 GHz — and via inductance becomes the thing to worry about instead. A package via is short, thin, and carries current into a die with enormous di/dt, so the L·di/dt it develops is a power integrity problem rather than a signal one. Same structure, different dominant term. See Simultaneous Switching Noise and Ground Bounce.

In the real world

Vias are where signal integrity stops being a 2D problem. Everything else on this section of the site can be reasoned about from a cross-section: trace width, height above plane, spacing to a neighbour. A via cannot — it is genuinely three-dimensional, it couples to every plane it passes, and its behaviour depends on the stackup as a whole rather than on any one layer.

Via models are therefore worth checking when a simulation and measurement diverge. A channel built from an accurate 2D trace model and a crude via model will match well at low frequency and diverge exactly where the vias start to matter. If your correlation falls apart above a few gigahertz, look at the vias before you look at the laminate.