Start / interview guide
Signal and Power Integrity Interview Guide
Most signal and power integrity interviews test whether you understand the physics well enough to reason about a problem you have not seen, not whether you remember a specification’s numbers. They draw on almost every topic on this site, and lean towards signal integrity or power integrity depending on the role. This guide maps what gets asked to the pages that teach it, lists the estimates you should be able to make in your head, and leads to two question banks with layered answers.
How SI and PI interviews tend to run
This describes the usual shape, not any one company’s process, and the shape varies between companies; a few stages recur. A first conversation checks fundamentals: what characteristic impedance is, why reflections happen, what a decoupling capacitor really does. A technical round then goes deep on one side, signal or power, depending on the role, usually by asking you to reason through a mechanism and then pushing on it with follow-ups. Many interviews also include a design or debug discussion, where you are given a symptom and asked how you would find the cause, and a walk through your own work.
The follow-ups are where interviews are decided. A first answer that names the right effect is expected; what separates candidates is whether they can say why it happens, put a number on it, and say what they would do about it. That is why each question in the two banks is answered in three layers.
What gets asked, and where to read it
| Area | What gets probed | Read |
|---|---|---|
| Transmission lines | what sets impedance, when a trace is a line, what a discontinuity does, which termination to use | impedance · critical length · reflections · termination · TDR |
| Edges, loss and ISI | why the edge and not the clock sets bandwidth, skin and dielectric loss, how loss turns into ISI | edge rate · loss · ISI |
| Eyes, jitter and BER | what an eye shows and hides, jitter decomposition, BER extrapolation | eye diagrams · jitter · bathtubs |
| Coupling and return paths | NEXT against FEXT, where return current flows, splits, slots and vias | crosstalk · coupling · return paths · vias |
| Differential signalling and S-parameters | modes, mode conversion, reading S11 and S21, passivity and causality | differential · S-parameters |
| Channels and receivers | budgets, CTLE, FFE, DFE, CDR, NRZ against PAM4 | budgets · eye closure · equalisation · CDR · NRZ vs PAM4 |
| Package and board | stackups, breakout, layer changes, connectors, tolerance | stackups · escape routing · layer changes · connectors · tolerance · packages |
| The PDN | what it must do, target impedance, the three droops, decoupling, anti-resonance, planes | the PDN · target impedance · three droops · decoupling · anti-resonance · planes · MLCC derating |
| PI at the silicon | the regulator’s loop, DC drop, switching noise, supply-induced jitter, chip–package–system analysis | VRM loop · IR drop · SSN · PSIJ · CPS analysis |
| Method | how a channel or PDN is simulated, measured, correlated and reported | simulation flow · IBIS-AMI · statistical vs time domain · de-embedding · field solvers · measurement · correlation · reporting margin · debug |
| Interfaces, as worked examples | how the concepts combine on a real bus; the specification’s numbers are rarely the question | DDR5 · LPDDR6 · PCIe 4/5 · PCIe 6 |
Numbers to estimate in your head
Interviewers like quick estimates, because they show that the formulas mean something to you. Try each one before opening it. Every answer links to the calculator or page that does it properly.
A 10 Gb/s NRZ link: how long is one bit, and what is its Nyquist frequency?
One UI is the inverse of the bit rate: 100 ps. NRZ’s fastest pattern, 1010…, repeats every two bits, so the Nyquist frequency is half the bit rate: 5 GHz.
A 50 ps edge: up to what frequency does its spectrum matter?
The knee frequency, about 0.5/tr: 10 GHz. The −3 dB bandwidth of a single pole with that rise time is 0.35/tr, 7 GHz. The clock rate does not enter.
How fast does a signal travel on FR-4?
About 170 ps per inch in stripline, roughly 6.7 ps/mm, set by Dk near 4. A microstrip is faster, about 147 ps per inch, because part of its field is in air.
A 100 ps edge on stripline: when is the trace a transmission line?
When the round trip exceeds about a third of the rise time, 2Td > tr/3, so the critical length is tr/(6·tpd): about 2.5 mm at 6.7 ps/mm. Almost every high-speed net is longer.
A 50 Ω line into 75 Ω, and into 30 Ω: what reflects?
Γ = (ZL − Z0)/(ZL + Z0): +0.2 into 75 Ω, −0.25 into 30 Ω. An open gives +1, a short −1, a match 0.
20 dB of return loss: how big is the reflection?
|Γ| = 10−RL/20 = 0.1, a tenth of the incident voltage, and a VSWR of about 1.22.
−3 dB, −6 dB, −20 dB: what fractions are they?
In voltage: −6 dB is a half, −20 dB a tenth, −3 dB about 0.707. In power, −3 dB is a half and −10 dB a tenth.
How deep does current flow in copper at 1 GHz?
The skin depth is about 2.06 µm, and it shrinks as 1/√f: about 0.65 µm at 10 GHz. That is why conductor loss grows as √f.
A 60 mil via stub in Dk 4: where does it notch the channel?
An open stub resonates when it is a quarter wavelength long: f = c/(4·L·√Dk), about 24.6 GHz. Halve the stub and the notch doubles in frequency; backdrilling moves it out of band.
A 0.8 V rail, 3% ripple, a 20 A load step: what impedance must the PDN hold?
Ztarget = Vdd·ripple/ΔI = 0.8 × 0.03 / 20 = 1.2 mΩ, across the band where that step has energy.
A 100 nF capacitor with 1.6 nH of loop inductance: where does it stop helping?
At its self-resonance, 1/(2π√LC): about 12.6 MHz. Above it the capacitor is an inductor, and only less inductance, not more capacitance, lowers the impedance.
1 nH of shared return inductance, 20 mA switching in 50 ps: how much ground bounce?
V = L·di/dt, taking di/dt as the current over the edge time: 1 nH × 20 mA / 50 ps = 0.4 V for one driver. Several drivers through the same inductance add, and a smooth edge peaks higher than the average.
At a BER of 10−12, how many sigma of random jitter do you allow?
Q ≈ 7.03 each side, so total jitter is deterministic jitter plus about 14.07 × the rms random jitter.
PAM4 against NRZ at the same swing: how big is each eye?
A third of the height: three eyes share the swing, a penalty of about 9.5 dB, paid back only if halving the symbol rate saves more loss than that.
A 1 pF via on a 50 Ω line: how long does its dip on a TDR last?
It behaves like an RC with time constant Z0C/2 = 25 ps, and the area of the dip in ρ·time is the same 25 ps for any edge.
Two capacitors in parallel: where does the anti-resonance peak sit, and what sets its height?
Between their self-resonances, where one capacitor’s inductance resonates with the other’s capacitance. Its height is set by the resistance in the loop: the closer the ESR is to √(L/C), the flatter the curve.
How to answer well
- Start with the mechanism in one sentence. “Part of the wave reflects because the line suddenly has a different ratio of voltage to current” beats a list of formulas.
- Then the equation or the number. Γ = (ZL − Z0)/(ZL + Z0), and what it gives for the case in front of you.
- Then the trade-off. Every fix costs something: power, swing, area, layers, margin elsewhere. Saying what it costs is what makes an answer sound like engineering.
- Then how you would check it. A simulation, a TDR, a VNA sweep, a probe on the rail. Saying how you would find out shows that you can tell what you know from what you expect.
- When you don’t know, say what you would do. “I haven’t worked with that, but I would expect… and I would confirm it by…” is a good answer; a guess presented as a fact is not.
For “tell me about a hard problem you solved”, use the same order: the symptom, how you narrowed the cause down, the root cause with the evidence for it, the fix and what it cost, and what you would do differently. The debug playbook is a good model of the reasoning interviewers want to hear.
Prepare one story of your own
“Tell me about a problem you solved” is the one question you can prepare completely, because the material is yours. Choose two problems, one signal integrity and one power integrity if you have them, and write each one in six short answers:
- The symptom. What was observed, where, and under what conditions? One sentence a non-specialist could follow.
- The first suspects. What did you expect the cause to be, and why?
- The narrowing. Which measurements or simulations ruled causes in or out, in what order, and what did each cost?
- The root cause, and the evidence. What showed it was the cause rather than a coincidence, and what would you have seen if it were not?
- The fix, and its price. Swing, power, area, layers, schedule, or margin somewhere else.
- In hindsight. What would have caught it earlier, and what do you do differently now?
Practise telling it in two minutes, then in thirty seconds. Describe the mechanism and the method; there is no need to name a product, a customer or any figure you are not free to share, and the reasoning is what the story is for.
Common misconceptions, and what to say instead
Each of these has a grain of truth, which is why it is tempting. The better answer keeps that grain and adds the condition under which it stops being true.
- “It’s a 100 MHz clock, so it isn’t a transmission line.” The edge decides, not the clock: a 100 MHz clock with a 100 ps edge has energy to several gigahertz and its traces ring like any fast link. Why.
- “Add more decoupling capacitors.” Above a few tens of megahertz a capacitor is its mounting inductance, and mixed values can raise a peak between them. The fix is usually less inductance or damping, chosen against a target impedance. Why.
- “A differential pair doesn’t need a reference plane.” Its odd mode carries the signal, but any imbalance creates common-mode current that still needs a return, and a pair crossing a split radiates and converts modes. Why.
- “Terminate everything to match.” Parallel termination burns DC power; series termination suits point-to-point nets and leaves the line unterminated at the far end; on-die termination is switched in only when it is needed. The right choice depends on topology, power and swing. Why.
- “The stackup says 50 Ω, so the channel is 50 Ω.” Vias, pads, connectors, packages and etch tolerance all add discontinuities, and a TDR of the real channel rarely reads flat. Why.
- “Spacing fixes crosstalk.” Spacing helps, but so do a closer reference plane, shorter coupled length for far-end crosstalk, stripline instead of microstrip, slower edges and avoiding gaps in the return path. Why.
- “The simulated eye is open, so we have margin.” An eye from a few thousand bits says little about 10−12; margin needs jitter and noise extrapolated, corners, and a stated reference plane. Why.
- “A DFE can fix any ISI.” It cancels only post-cursor ISI, only as many bits as it has taps, only within its tap ranges, and a wrong decision feeds back. Why.
- “Keep the PDN below target from DC to infinity.” The board cannot control impedance above the frequency where package and on-die capacitance take over; each part of the PDN owns a band. Why.
A study plan
One evening. The numbers above, the common misconceptions, and the first ten questions in each bank.
Four weeks.
- Week 1, foundations. Impedance, reflections, termination, return paths, edges and bandwidth, and the travelling-waves lab.
- Week 2, the channel. Loss, ISI, eyes, jitter, crosstalk, S-parameters, equalisation, and the channel lab.
- Week 3, power. The PDN, target impedance, the three droops, decoupling, anti-resonance, supply-induced jitter, and the PDN lab.
- Week 4, practice. Stackups, vias, simulation flow, measurement, debug, one interface page as a worked example, and both question banks out loud.
The learning paths cover the same ground in a guided order, with an experiment at each step.