DDR5 Signal Integrity: Fly-by, ODT, DFE and Training

The panel above is one data bit on a two-slot server bus. The left chart is a map of the wiring against time: distance runs across, from the controller to the DRAM being written, with the branch to the other slot as its own strip, and time runs down. A travelling bit is a diagonal stripe. Where it meets a change of impedance, part of it turns round, and a reflection is a stripe running the other way. The column on the right is the same bit as the receiver sees it, on the same time axis. Every bump in that column is a stripe arriving. Most of this page is about where those stripes come from and what DDR5 does about each of them.

What DDR5 is

DDR5 SDRAM is JEDEC’s fifth double-data-rate memory generation, the main memory of servers, desktops and laptops. The standard is JESD79-5, first published in 2020 and revised since: JESD79-5C (April 2024) extended the timing definitions to 8800 MT/s, and the current edition, JESD79-5D, appeared in November 2025. Parts and platforms are qualified at particular speed bins, so the bin a given system runs is a property of the parts and the board, not of the generation.

At 3200 MT/s a bit lasts 312.5 ps; at 4800, 208 ps; at 6400, 156 ps; at 8800, 114 ps. The clock runs at half the transfer rate, so at 6400 MT/s one clock period, t_CK, is 312.5 ps. Keep those numbers in mind: the wiring on this page is measured in hundreds of picoseconds, so every reflection lands one or more whole bits late.

Two things have not changed, and they set the whole problem. The data lines are still single-ended, one wire per bit, because a 72- or 80-bit bus cannot afford a second wire each. And they still pass through a connector, onto a module the board designer did not lay out, often sharing their wire with a second module. If you are weighing DDR5 against LPDDR5X, the comparison is further down.

The module, from above

Two wiring styles on one module, for two different reasons. The data bus carries the fast signals, so it gets the cleanest possible path: point to point, short, one DRAM per wire. The command bus is slower but goes to every DRAM, and a star that split it ten ways would be a stub forest; a fly-by, one line passing each DRAM in turn, has no stubs longer than a via. The price is that the clock reaches each DRAM at a different time, which is what write leveling, further down, exists to fix.

The RCD also changes the command bus’s shape. The controller sends it 7 command and address pins per subchannel at double data rate; it drives the DRAMs with 14 pins at single data rate. Half the pins on the mainboard, at twice the rate, and the freed pins became grounds: the DDR5 RDIMM edge has noticeably more V_SS pins than DDR4’s, because every signal on it is referenced to ground.

The signal: pseudo-open drain

DDR5’s data lines use pseudo-open-drain (POD) signalling, at 1.1 V. Read the figure as a voltage divider: every termination on the wire, in parallel, against the driver. That one fact explains a lot of what the panel does. Terminate more strongly, or terminate in two places at once, and the swing shrinks. Terminate less, and the swing grows but reflections are absorbed less well. Every termination choice on a DDR5 bus trades those two against each other.

Because the reference is internal and adjustable, the eye’s vertical centre is not a design value but a trained one. A VrefDQ step is 0.5% of V_DDQ, 5.5 mV, fine against a few-hundred millivolt swing.

Two DIMMs on one wire

A server board usually has two slots per channel, and the data line runs from the controller past the first slot to the second: a daisy chain. With both slots filled, a write to the near DIMM still sends part of every bit down the line to the far one. At slot 1 the bit meets a junction. Some of it goes up into the near DIMM, where it was meant to go; some of it carries on to slot 2, and whatever is not absorbed there comes back, a few hundred picoseconds later, and arrives at the near DRAM on top of a later bit.

The arithmetic is worth doing once. In the panel’s model the far branch, from slot 1 to the far DRAM, is 10 mm of trace between slots (67 ps), the connector (25 ps), 20 mm on the module (134 ps) and the DRAM package (30 ps): 256 ps one way and 512 ps there and back. At 4800 MT/s that echo lands 2.5 bits after the bit that launched it; at 6400, 3.3 bits; at 8800, 4.5. The echo itself does not change. What changes is which later bit it lands on.

There is a second echo, and in the panel’s first scenario it is the larger one. The near DIMM’s own DRAM is lightly terminated there (RTT_WR 240 Ω), so it sends much of each bit back down its own branch. At slot 1 that reflection meets the mainboard and the far branch in parallel, a lower impedance than the line it arrives on, so it turns round inverted and reaches the DRAM again one round trip of the near branch later: connector, module trace and package, 189 ps each way and 378 ps there and back, about 1.8 bits at 4800 MT/s. That is the deep dip just after the cursor in the panel’s receiver column. Move the far slot and it stays where it is; terminate the target more strongly and it nearly vanishes, at the price of swing.

Choose “Other DIMM unterminated” in the panel and watch the far strip: the share of the bit that enters it bounces between the open end and the junction, a zig-zag that keeps leaking back into the path. The eye shuts. Turn the other DIMM’s termination back on and the zig-zag fades on its first trip, because the far DRAM now absorbs most of what reaches it.

Board makers’ manuals name the slot to fill first when a channel has one DIMM; ASUS’s, for example, says DIMM_A2 and gives no reason. The panel gives a likely one for a daisy-chained layout: the far slot leaves the shorter stub. Which slot is “far” depends on the board’s routing, so follow the manual rather than the slot number.

Termination is a schedule, not a resistor

On a DDR5 bus every DRAM carries its own on-die termination (ODT), programmable in steps of a 240 Ω reference: 240, 120, 80, 60, 48, 40 and 34 Ω, or off. What makes it powerful is that a DRAM applies a different value depending on what the bus is doing at that moment:

A non-target DRAM learns that a transfer is under way from a command addressed to it, so the controller can switch it between its nominal and park values burst by burst. The board designer’s job is no longer to pick a resistor; it is to find the combination that leaves the best eye at every receiver, for every rank, in both directions.

That is what the panel’s Termination sweep does: it runs the bus with every pair of target and other-DIMM values, 64 simulations, and colours each by its worst-case eye height. Look for the shape of the answer rather than one number. Off on the other DIMM is always bad, because it leaves an open stub. Very strong termination everywhere is never best, because it divides the swing away. The best settings lie between those two, and they move when the data rate, the slot spacing or the target changes. That is why ODT values are swept, not calculated.

The DRAM equalises its own input

DDR4’s DRAM had no equaliser at all. DDR5’s has a decision feedback equaliser (DFE) on every data input, because at these rates the reflections described above no longer fit inside one bit. A DFE works on what the receiver has already decided: if the previous bit was a 1, and a 1 is known to leave a certain residue on the bit after it, subtract that residue before deciding the next one. Because it subtracts a known quantity rather than boosting high frequencies, it does not amplify noise, which is why it suits a reflective channel; a public DDR5 data sheet makes the same point.

Two limits follow, and the panel shows both. A DFE has four taps, so it reaches the four bits after the cursor and no further. The near DIMM’s own 378 ps echo lands on the second or third bit at these rates, inside its reach; the far branch’s 512 ps echo, if the far DIMM returns much of it, lands four and a half bits late at 8800 MT/s, between taps 4 and 5, and only part of it can be cancelled. And each tap has a range: a reflection larger than the tap’s limit is cancelled only up to it. In the “Two DIMMs at 6400” scenario the near DIMM’s echo is the third post-cursor and far larger than tap 3’s 60 mV, and taps 2 to 4 together may not exceed 60 mV either; the DFE taps readout shows what training was allowed to set, and the eye shows what was left.

The map shows where the DFE’s reach ends. The shaded band in the receiver column covers the four post-cursors it corrects; anything arriving below the band is past it. Making the stub shorter moves its echo up into the band. Making the bus faster pushes it down and out.

With the DFE on, the panel’s eye is what the slicer sees: the input after the summer has subtracted each correction. That eye has seams half a bit either side of the sampling instant, where the correction for one bit gives way to the next, and it is only meaningful between them. It also sits lower than the eye at the pin. With its post-cursors removed, a 0 settles at the same level whatever came before it and a 1 at that level plus the cursor, so training finds the reference near the middle of the cursor rather than the middle of the full swing.

The fly-by and write leveling

Back to the command bus. The RCD drives the clock along the fly-by, so DRAM 0 sees each clock edge first and DRAM 4 last. Each DRAM’s input capacitance also slows the line it hangs on. A line loaded with a capacitance C_load every pitch behaves like a slower line of lower impedance:

With a 50 Ω line at 6.7 ps/mm and DRAMs 12 mm apart, each pitch of line holds 1.61 pF. Add 1 pF of DRAM input and the line slows by a factor of 1.27: each gap now takes 102 ps instead of 80, the line looks like 39.3 Ω, and the clock reaches the fifth DRAM of the subchannel 410 ps after the first. At 6400 MT/s that is 1.31 clock periods; at 8800, 1.80. A designer who wants the loaded line to land at a chosen impedance routes it above that impedance to begin with.

The data strobes, meanwhile, come straight up from the edge connector and arrive at every DRAM at about the same time. If the controller launched every byte lane’s strobe the same way, it would be on time for DRAM 0 and hundreds of picoseconds early for DRAM 4. Write leveling fixes that per lane. Untick it in the panel to see the error it removes.

DDR5 adds a second step. Inside the DRAM, the path from the strobe pin to where data is captured is not matched to the clock’s path, so lining the strobe up with the clock at the pins is not quite enough. An internal cycle alignment step, also driven from the controller, adjusts the DRAM’s own write timing to absorb that difference. Between them, every lane’s strobe ends up aligned in phase and in cycle with its own DRAM’s clock, however far along the fly-by that DRAM sits.

The same chain explains DDR5’s command-bus termination. With the termination on the DRAM die, every DRAM on the chain has one, and a strap pin decides which group’s setting it uses: the DRAMs along the chain take a weak setting or none, and the last one, at the end of the fly-by, a strong one. Choose “No end termination” above to see what the last DRAM would otherwise do to everyone else’s clock.

Training: the controller never sees the eye

Everything so far assumes someone knows where the eye is. Nobody does. The controller has no oscilloscope at the DRAM’s pins; it has a delay line on each strobe, a register for each DRAM’s VrefDQ, and the ability to write a pattern and read it back. Training is the process of finding the eye with only those, at every power-up and again when the temperature moves.

The panel’s What training sees view is that process in one picture, a shmoo. For every strobe delay step and every VrefDQ step, send a PRBS burst and record pass or fail. The pass region is the eye as the controller knows it: blockier than the true eye, because Vref moves in 5.5 mV steps, and ragged at its edges, because real noise and jitter make marginal settings pass sometimes and fail sometimes. A trainer then picks a point inside it. The one in the panel takes the Vref with the widest passing run of delays and the middle of that run, one common rule among several.

DDR5 trains in stages, each one making the next possible: chip select and command/address first (otherwise no command can be trusted), then write leveling, then read training with patterns the DRAM itself generates, including an LFSR pseudo-random one, then write training, VrefDQ per bit and the DFE taps. A duty-cycle adjuster in the DRAM corrects the read strobe’s duty cycle, and a strobe interval oscillator lets the controller measure how far the DRAM’s internal strobe delay has drifted, so it can decide when to retrain.

What a pass means

The target is a raw bit error ratio of 10⁻¹⁶ per lane, before any correction. That is hard to picture until it is turned into time: at 6400 MT/s one lane at 10⁻¹⁶ errs about once every 18 days, and the 80 data lanes of one DIMM together about once every 5.4 hours. That is why server memory carries ECC on top, and why DDR5 adds CRC on reads as well as writes and single-error correction inside the DRAM.

Nobody measures 10⁻¹⁶ directly. Receiver and transmitter limits are validated at 10⁻⁹, which at 99.5% confidence needs 5.3 × 10⁹ bits without an error (−ln(0.005)/10⁻⁹), 0.83 s of one lane at 6400 MT/s, and the eye is extrapolated from there. The DRAM’s receiver is tested with a stressed eye: a reference channel plus injected jitter and noise, adjusted until the eye at the slicer, after the DFE, is just the specified height and width. In the data sheet read for this page that is 95 mV by 0.25 UI at 3200 MT/s, narrowing to 57.5 mV by 0.23 UI at 6400, with the higher bins still to be defined in that revision. The panel draws that diamond on the eye. It is a statement about the receiver, not a mask for the channel: a channel whose eye at the slicer is bigger than the diamond, with everything else that closes it accounted for, is one the receiver is specified to handle.

The panel’s two eye readouts differ for a reason. “Eye, PRBS” is the opening of a 2047-bit pattern; “worst case” is the peak-distortion bound, the eye of the worst possible bit sequence for this pulse response. The worst sequence may never occur in a training pattern, which is one reason a bus can train well and still fail later on real data.

LPDDR5X vs DDR5

LPDDR5X and DDR5 are JEDEC memories of the same era, and from far away they look alike: single-ended data, a strobe travelling with it, everything trained at power-up. The difference is where each one lives, and nearly every electrical choice follows from that. LPDDR5X is soldered next to the processor, or stacked on its package, so its channel is a few centimetres of board with nothing in the way. DDR5 sits on a module in a socket, so its channel crosses a mainboard and a connector and often shares its wire with a second module.

The swing follows the channel. LPDDR5X signals at a V_DDQ of 0.5 V (0.45 V on some parts) with low-voltage swing-terminated logic (LVSTL), and can drop to 0.3 V with termination off. That is affordable only because its channel is short and private: there is little loss, no connector and no stub to eat the margin. DDR5 keeps a 1.1 V pseudo-open-drain bus, because its signal has to survive the connector, the shared wire and the terminations along it.

The clocking differs. LPDDR5X separates a slow command clock from a fast write data clock that runs at two or four times its rate and only when it is needed; reads come back with their own strobe. DDR5 uses one differential strobe per byte, driven by whichever end is sending. Both make the data source-synchronous, so delay the data and its strobe share cancels, and both train the strobe into the eye at power-up.

What limits each is different. On LPDDR5X the enemies are crosstalk and simultaneous switching noise in a dense escape from a fine-pitch package, and skew between bits; the LPDDR5X page works through that budget. On DDR5 they are reflections from the connector and from the other module, the choice of termination for each DRAM, and the fly-by skew on the module: this page.

The line between them is blurring. JEDEC’s CAMM2 standard puts either memory on a compression-attached module with a common connector and different pinouts, and JEDEC aims LPDDR5/5X CAMM2s at notebooks and some server segments. A CAMM2 is still a connector, but a short, flat one, so it buys LPDDR5X upgradability while keeping most of its channel. The choice that remains is the old one: LPDDR5X where power and speed per watt rule and the capacity is fixed at build, DDR5 where capacity, upgrades and ECC matter and the board can pay for a longer channel.

In the real world

Two DIMMs per channel costs speed. Server platforms commonly qualify a lower data rate with two DIMMs per channel than with one, and the panel shows why: the second DIMM’s stub, terminated or not, takes a share of every bit and returns some of it late. Check the platform’s population rules before assuming the headline speed.

Client modules above 6400 MT/s add a clock driver. On an unbuffered DIMM the controller drives the DRAMs’ clock directly, through the connector and along the fly-by. JEDEC’s clocked UDIMM and SODIMM (JESD323 and JESD324) put a clock driver on the module that regenerates the clock locally, which JEDEC presents as the step from 6400 toward 7200 MT/s on client modules. Command and address still come from the controller, so the rest of this page still applies.

Power is now on the module. The PMIC regulates V_DD, V_DDQ and V_PP next to the DRAMs, from 12 V on server modules and 5 V on client ones. That shortens the DRAM’s power delivery path, and it means the module’s own regulator and decoupling are part of every data eye’s noise. A DDR5 signal-integrity simulation that ignores the module’s power network ignores a source of jitter that DDR4 put on the mainboard.

Debug starts from the training results. The controller knows, for every DRAM and every lane, where training landed and how wide the passing region was. A lane whose window is narrower than its neighbours’ points at its own routing; a whole DIMM that is narrow points at the slot, the population or the termination; a window that shrinks as the system warms points at timing drift. All of it is available without probing a pin.

Where the numbers come from

• JEDEC JESD79-5D, DDR5 SDRAM (Nov 2025), and JEDEC’s JESD79-5C announcement (Apr 2024) — editions and the 8800 MT/s timing extension; ledger C-35 and C-36. The standard itself is sold and has not been read.
• Micron, DDR5 SDRAM core data sheet (Rev. D, Oct 2022, stated JESD79-5B compliant) — supply voltages, ODT and driver values, VrefDQ range and step, DFE tap ranges, stressed-eye limits, BER requirements, write leveling; ledger C-37 to C-43.
• Micron white papers and technical briefs: “Introducing Micron DDR5 SDRAM: More Than a Generational Update”, “DDR5 SDRAM: New Features”, “DDR5: Key Module Features” and “DDR5: Client Module Features” — the DDR4 comparison, subchannels, PMIC input voltages, the RCD’s command bus and CA termination groups; ledger C-44 to C-49.
• JEDEC clocked UDIMM and SODIMM (JESD323, JESD324), as announced in October 2024 — ledger C-50.
• Micron, x32 automotive LPDDR5X data sheet and JEDEC’s CAMM2 announcement (Dec 2023) — the LPDDR5X side of the comparison; ledger C-53 and C-54, with C-2a, C-3 and C-4a from the LPDDR5X page.
• ASUS support FAQ, “How to install DRAM on motherboard” — the slot to fill first; ledger C-51.
• Platform memory population guides — that two DIMMs per channel usually run slower; ledger C-52, awaiting a source.

Related

• LPDDR5/5X Signal Integrity: WCK, ODT and Training — the mobile cousin: point to point, no DIMM
• Transmission-Line Reflections and Ringing — what one boundary does to a step
• TDR (Time-Domain Reflectometry): Reading PCB Impedance — reading a stub and a connector on a trace
• Termination Schemes: Series, Parallel, Thevenin and AC — why a terminated line stops ringing
• SerDes Equalization: CTLE, FFE, DFE and CDR — the DFE in a serial receiver
• Simultaneous Switching Noise and Ground Bounce — what an 80-bit bus switching together does to its reference