Package & board / 04
Stitching Vias and PCB Layer Transitions
When a signal changes layer, its return current has to change plane too — and unlike the signal, the return has no via of its own unless you gave it one. Whether a layer change costs you nothing or ruins a channel depends entirely on what the return can do at that point.
When a PCB layout designer drops a via to route a high-speed trace from a top microstrip layer down to an inner stripline layer, the EDA software renders a clean, solid cylinder and marks the net complete. But in electromagnetic physics, a high-speed signal never travels as an isolated current down a lone wire; it travels as an electromagnetic wave guided between the trace and its immediate reference plane. For every milliampere of signal current surging forward through the conductor, an equal and opposite return current travels directly beneath it in the adjacent copper plane.
When the signal hits a via and plunges through the vertical thickness of the PCB, the forward current has an engineered copper path. But the return current faces a crisis: it cannot jump across the dielectric void between reference planes. If the signal transitions between layers that reference different planes, the return current must find its own vertical bridge to follow along.
If you do not deliberately design that vertical return path, the return current will wander laterally across the board until it finds the nearest path of opportunity — a distant ground via, a mounting hole, or a decoupling capacitor. That detour blows open the high-frequency current loop area (A). Because loop inductance scales with enclosed area (L ∝ μ · Area / length), this detour creates a localized inductive discontinuity that distorts the signal edge, injects severe ground bounce into neighboring nets, and turns the via into a miniature dipole antenna that sprays electromagnetic radiation.
Follow the return, not the signal
The signal's path through a layer change is obvious: down a via, out on a different layer. That is what the routing tool shows you and it is the uninteresting half.
The return current has the harder job. It was flowing in the plane directly under the trace; now the trace is somewhere else, referenced to a different plane, and the return has to get from the first plane to the second. There is no via for it unless you placed one.
A useful question at each transition is: what path does the return current take here, and how big is the loop it has to make? Answer that and the three cases below sort themselves out.
Three cases, three costs
Track the return current, not the signal, and layer transitions sort themselves into three categories:
- Case 1: Same reference plane on both sides (GND → same GND). A signal moving between two routing layers that share the exact same reference plane — for example, transitioning from Layer 1 (microstrip over Layer 2 ground) to Layer 3 (stripline under Layer 2 ground) — is nearly benign. The return current does not need to change planes; it simply wraps around the perimeter of the via's antipad clearance hole, flowing from the top copper skin of the plane to the bottom copper skin. The added loop inductance is minimal (typically < 0.2 nH), and no stitching vias are required.
- Case 2: Two different planes, both ground (GND1 → GND2). When a signal transitions between two layers referenced to different ground planes (e.g. Layer 3 referenced to Layer 2 GND, plunging to Layer 10 referenced to Layer 9 GND), the return current is trapped on Layer 2 until it finds a vertical connection to Layer 9. You must provide that path by placing a dedicated ground stitching via immediately adjacent to the signal via (within 20 to 30 mils). Placing it close minimizes the physical loop area and allows the mutual inductance between the signal and ground vias to partially cancel the via barrel inductance. If that stitching via is placed 150 mils away, the return loop adds roughly 1 nH of parasitic inductance — enough to cause a severe reflection notch at 10 GHz.
- Case 3: Two different planes of different nets (GND → Power). This is the most hazardous transition on a board. If a signal transitions from a layer referenced to a ground plane to one referenced to a VDD power plane, you cannot simply drop a stitching via between them — doing so would short power directly to ground. The return current has only two ways to cross: through the inter-plane capacitance of the power/ground pair, or through a surface-mounted stitching capacitor. But any real capacitor carries mounting pad and via loop inductance (ESL, typically 0.5 to 1.2 nH). That inductance sits in direct series with your high-speed signal's return path. Even worse, the return current injects high-frequency switching noise directly into the power rail, creating supply ripple that modulates other components. The best design rule for GND-to-Power layer transitions is simple: never route high-speed signals across them.
Watch the return current spread
The three cases are claims about where a current goes. The panel below lets you watch it go. It solves Maxwell’s equations for the space between two planes 0.2 mm apart on a 100 × 60 mm board and draws the voltage between the planes as the height of a sheet, flat while the planes sit at the same potential. The signal via changes reference with a 10 mA edge, so its return current has to cross from one plane to the other at that point.
At the signal via itself, the return current rises from 0 to 10 mA in 60 ps: a peak rate of about 170 mA per nanosecond. Forcing that current across the gap kicks up a voltage between the planes right at the via, a spike of a few tens of millivolts that lasts about as long as the edge. It is set by how fast the current changes and by the inductance of whatever path the return can find, so a stitching via close by shrinks it, and so does a slower edge. The panel shows the current, its rate and that voltage beside the via as the edge plays out.
If there is no via to carry it, the return current crosses through the capacitance between the planes. That launches a ripple that spreads at c/√Dk, about 150 mm per nanosecond for a Dk of 4, and reflects off the board edges. A victim via 50 mm away sees the first pass, then every reflection after it, because the plane pair is a resonant cavity and goes on ringing for nanoseconds.
Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.
Some things to try, roughly in order:
- Drop a stitching via right beside the signal via. The ripple shrinks, and the dashed trace of the previous run stands above the new one at the victim.
- Drag the stitching via away. The victim noise climbs back as the gap grows. This is the “within a few tens of mils” rule, made visible.
- Surround the signal via with four stitching vias. The return closes in a loop much smaller than a wavelength, and very little reaches the rest of the board.
- Switch to GND to PWR. Each click now places a 100 nF capacitor with 0.7 nH of mounting inductance. At 1 GHz that inductance alone is 4.4 Ω, far more than the plane pair it is meant to short, so the capacitor barely changes the ringing.
- Slow the edge to 300 ps. The upper resonances fade out of the spectrum (the shaded band is where the edge has too little energy to measure the board), and the ringing becomes smoother.
- Click the four mounting holes away. With nothing left between the planes, the spectrum’s peaks land on the dotted lines, the closed-form modes of a bare rectangular cavity. Every via you put back moves them.
Rules that follow
A handful of layout conventions fall straight out of the three cases, and they are worth stating as rules because they are cheap to apply and expensive to retrofit:
- Plan layer transitions in the stackup so that high-speed signals move between layers that share a reference, or between two ground-referenced layers. This is a stackup decision, and it is free if made early.
- Place a ground via adjacent to every high-speed signal via — for differential pairs, ideally two, symmetrically, so the pair stays balanced through the transition.
- Avoid changing reference from ground to power on a high-speed net. If it is unavoidable, put the stitching capacitor as close as the footprint allows and accept that it is a compromise.
- Keep the number of transitions down. Each one is a discontinuity and a potential stub, and they add up in a way no single one suggests.
The reason this is worth attention out of proportion to its apparent complexity: nothing in the schematic, the netlist or the DRC shows you a return path. A design can be electrically correct by every automated check and still route a signal across three plane changes with no stitching, and the only thing that catches it is somebody deliberately looking.
Why this decides how your board behaves
- A missing return path is a series inductance. At a fast edge's knee frequency, a couple of nanohenries is tens of ohms in a 50 Ω system — a real discontinuity that shows on a TDR and in S11.
- It couples nets that share the detour. Several signals whose returns are all forced through the same stitching via are coupled through its inductance, however far apart their traces run.
- It is invisible to the netlist. No connectivity check flags a missing return via, because nothing is disconnected. The board is correct and the channel is not.
- The ground-to-power case is categorically worse. There is no DC path at all, so the return goes through plane capacitance — and above the point where that stops being effective, through whatever loop it can find.
What to do about it
Prefer transitions that keep the same reference. A signal moving from above a plane to below the same plane is nearly free — the return simply moves from one face to the other. Plan the layer assignment so that high-speed transitions land this way.
Where the planes differ but are both ground, place a stitching via — close. Within a few tens of mils. A stitching via on the other side of a component leaves a much larger return loop.
Where the planes are different nets, place a stitching capacitor at the transition and accept that it is a compromise. Its own mounting inductance limits how well it works, which is why this case is worth designing out rather than fixing.
Count return vias in review. One per signal via at a plane change, as a checklist item. It is the cheapest insurance in board design.
- A TDR bump exactly at a layer change. Look for the return via. Its absence, or its distance, is the size of the bump.
- Crosstalk between nets that never run near each other. Find the shared stitching via or the shared plane opening.
- A channel that measures worse than the sum of its traces. Count the transitions and check each one's return path before re-examining the laminate.
- Emissions that change when you add ground stitching. Confirms a return-path loop was radiating.
Go deeper — estimating the cost, and why the capacitor case is worse than it looks
A useful field estimate: a return detour costs roughly 1 nH per millimetre of extra loop. Compare its reactance at your knee frequency against the line impedance and you have turned a judgement into arithmetic:
That comparison is worth doing out loud at a review, because "there is no return via here" sounds like a style comment until it is expressed in ohms.
Why the ground-to-power case is worse than it looks. The usual remedy is a stitching capacitor, and the instinct is that a capacitor is a short at high frequency. It is not — above its self-resonant frequency it is an inductance, and its mounting loop is in series with the very return path you were trying to shorten. So the capacitor helps in a band and stops helping above it, exactly where the fast edges live.
Which is why the plane-pair spacing matters here too: the two planes have distributed capacitance between them, and a thin dielectric provides a genuinely low-inductance high-frequency path that no discrete part can match. On a board with tightly coupled plane pairs the ground-to-power transition is much less bad than on one without.
And the antipad. Even with a return via present, the signal via's antipad is a hole in the plane that the return current has to route around. In a dense field those antipads merge, and the return path for the whole field is constrained by the resulting pattern rather than by any individual via. That is a breakout problem as much as a transition one.
How the panel works. Between two closely spaced planes, the only field that matters is the vertical electric field Ez and the magnetic field parallel to the planes. Maxwell’s equations then reduce exactly to two dimensions, and the voltage between the planes is V = Ezh. The panel steps them on a Yee grid of 0.5 mm cells, 24,000 cells for this board, with a time step of 95% of the stability limit:
A signal via that changes reference is a current source between the planes. A stitching via forces V = 0 in its cell. A stitching capacitor is a series R, L and C stepped alongside the field. The open board edge is treated as a magnetic wall, the textbook cavity boundary, so the closed-form resonances are
Loss comes from the laminate (tan δ = 0.02, a Q of 50) and from the plane copper, whose Q for a 0.2 mm pair is about 96 at 1 GHz and rises as √f. Together they give a plane-pair Q of about 33 at 1 GHz. A constant conductivity cannot hold Q roughly flat across frequency, so the solver uses one Debye pole plus a small conductivity, which holds the combined loss within 15% of that target from 0.3 to 6 GHz.
The model gate checks the solver against physics it does not contain. With no vias and no loss, its resonances land on fmn to within 0.5%. Field energy is conserved, the planes charge at exactly I/C, nothing arrives before the wavefront, swapping the two vias gives the same waveform, and the width of a resonance matches the loss tangent.
What it leaves out. The board is one plane pair, where a real stackup has several cavities coupled through every antipad. A via is a single 0.5 mm cell with no antipad and no barrel of its own above and below the pair. The edges do not radiate. The signal’s own transmission line is not modelled; its return current is imposed. So read the panel for mechanism and proportion — which via placement helps and roughly how much — not as a sign-off number for a particular board.
In the real world
Layer transitions are where the gap between a schematic and a board is widest. Everything is connected, every net passes DRC, and the high-frequency behaviour is decided by something that appears nowhere in the design data: the path a current takes through copper you did not think of as part of the net.
The habit that catches it is simple and manual — on the nets that matter, follow each transition and say out loud where the return goes. It takes minutes per net and it finds the problems that cost a spin.