LPDDR6 Signal Integrity: Wide NRZ and Sub-Channels

The panel asks the question JEDEC had to answer. Take a channel’s worth of bandwidth, 24 pins at the LPDDR6 rate, and carry it three ways through the same short channel at the same 250 mV swing: on LPDDR5X’s 16 data pins by running NRZ half as fast again, on the same 16 pins by sending PAM4, or on 24 pins at LPDDR6’s rate. The eyes show what each road keeps, and the allowance box in each shows what noise and jitter take. Try the scenarios: PAM4 is the first to close, faster NRZ the first to run out of time, and the wide road is still open.

LPDDR6 at a glance

How fast is LPDDR6?

LPDDR6 starts at 10.667 Gb/s per data pin, and its highest defined rate is 14.4 Gb/s. LPDDR5X reached 8533 MT/s in the editions read for this site and LPDDR5 6400 MT/s. The first LPDDR6 DRAMs, announced in 2026, run at about 10.7 Gb/s. More on the rates.

How much bandwidth does LPDDR6 have?

A 24-bit LPDDR6 channel carries 32.0 GB/s of raw bandwidth at 10.667 Gb/s per pin, 28.4 GB/s of it data once the metadata and protection bits are set aside, and 38.4 GB/s of data at 14.4 Gb/s. A 16-bit LPDDR5X channel at 8533 MT/s carries 17.1 GB/s. The full comparison.

Does LPDDR6 use PAM4?

No. LPDDR6 keeps two-level NRZ signalling and adds pins instead: twelve data pins per sub-channel and 24 per channel. At LPDDR’s quarter-volt swing, PAM4’s three eyes would each be a third of the height, and on a short, noisy channel that costs more than it saves. Why wide NRZ, and the panel at the top of this page, show the trade.

What voltage does LPDDR6 use?

The I/O supply, V_DDQ, stays at 0.5 V, or 0.3 V with termination off. The core supply splits into two rails that are both mandatory, V_DD2C at 1.0 V and V_DD2D at 0.875 V, and V_DD1 stays at 1.8 V.

What is new in LPDDR6?

Two 12-bit sub-channels per die with four command pins each; a 24-beat burst of 288 bits that carries metadata and DBI or link protection on the data pins, with no DMI pin; a much faster command clock; dynamic write non-target termination; an ALERT pin for faults; efficiency modes that run on one sub-channel’s I/O; and per-row activation counting against row hammer.

When is LPDDR6 available?

JEDEC published the standard, JESD209-6, in July 2025. SK hynix announced an LPDDR6 DRAM above 10.7 Gb/s in March 2026, with supply from the second half of that year.

LPDDR6 or DDR5?

They do different jobs. LPDDR6 is soldered next to the processor or stacked on its package, and wins on bandwidth per watt. DDR5 sits in sockets and wins on capacity, upgrades and ECC. The DDR5 page sets out that trade.

What LPDDR6 is

LPDDR6 is JEDEC’s sixth low-power DRAM generation, JESD209-6, published in July 2025. It is meant for phones and thin laptops, as its predecessors were, and JEDEC also names client computers, edge AI, automotive and servers. IP vendors describe a starting rate of 10.667 Gb/s per pin and a highest defined rate of 14.4 Gb/s; at those rates a bit lasts 93.75 ps and 69.4 ps. The first DRAMs announced, in 2026, run at about 10.7 Gb/s.

The unit interval by generation · the swing does not grow

One die, two sub-channels

An LPDDR6 die · two independent sub-channels of twelve data pins

LPDDR5X gave each die one 16-bit channel with seven command pins. LPDDR6 splits the die into two sub-channels of twelve data pins and four command pins each, with sixteen banks behind each. Four command pins are enough because each now runs much faster, of which more below. The access is smaller: one sub-channel burst carries 32 bytes of data, and the burst length can change on the fly to fetch 64.

Why wide NRZ, not PAM4

There are three ways to carry more bits per second down a bus: more pins, a faster rate on each, or more bits per symbol. GDDR7 and PCIe 6.0 took the third, with three- and four-level signalling. LPDDR6 took the first, and the panel above shows why.

A PAM4 receiver has to tell four levels apart in the same swing NRZ uses for two, so each of its three eyes is a third of the height before the channel has done anything: 83 mV of a 250 mV swing, a loss of 9.5 dB. PAM4 earns that back only when the channel is so lossy that halving the symbol rate matters more. An LPDDR channel is the opposite case: a few centimetres, a few decibels of loss, and a great deal of crosstalk and supply noise from a dense bus switching together. Noise is a fixed number of millivolts, so it takes the largest share of the smallest eye. Running NRZ faster on the same pins avoids that, but at 16 Gb/s or more the bit is so short that jitter and skew eat it, and the loss at the higher Nyquist frequency is larger.

Going wider keeps the rate, the levels and the receivers LPDDR already knew, and spends package balls and board routing instead. Samsung’s presentation at JEDEC’s LPDDR6 workshop framed the choice the same way, putting PAM4 at about half the signal-integrity margin and about one and a half times the I/O power for the same bandwidth. The panel’s model is simpler than a real channel, but it puts the three roads in the same order.

Faster everything else: the clocks

The command clock, CK, runs at 2.667 GHz at the starting rate, against 1.07 GHz on LPDDR5X. The write clock, WCK, runs at twice CK, 5.333 GHz, and data moves on both of its edges: the 10.667 Gb/s. LPDDR5X could run WCK at four times CK; LPDDR6 keeps only the 2:1 ratio, which is why CK had to speed up.

That changes the command bus from a slow side channel into a fast one. With four command pins sampled on both CK edges, each runs at 5.333 Gb/s, and a command bus that fast needs the same care as data: training to centre it, and on-die termination at the DRAM. JEDEC lists command and address parity among the standard’s reliability features, so a corrupted command can be caught rather than executed.

The 288-bit packet

Twelve pins by twenty-four beats · why the burst is BL24

An odd number of pins forces an odd burst. Twelve pins and the familiar burst of 16 would make 192 bits, which is not a cache-line-friendly size; twelve pins and a burst of 24 make 288, which holds 256 data bits with 32 to spare. Those spare bits are where LPDDR6 put features that used to need pins or did not exist.

The last sixteen are a choice, and only one choice can be made. They can carry DBI, which lowers I/O power by inverting groups of data that would otherwise send many 1s, or link protection, a code that detects or corrects bits flipped on the wire in either direction. A write error found by the DRAM is reported to the host on ALERT, a new shared pin. Power or protection: the panel below makes the power side of that choice concrete.

Why does a 1 cost energy? Because LPDDR terminates its data lines to ground. The next section is about that, but the panel already shows the consequence: data that is mostly 1s costs several times what mostly 0s costs, and DBI exists to keep the count of 1s at or below half. Choose “Link protection” and the protection is bought with that saving. At the starting rate each 1 on a pin costs about 0.29 pJ of termination energy in the panel’s model.

Termination: LVSTL, and who pays

LVSTL against POD · the termination decides which bit costs current

LPDDR6 keeps LPDDR5X’s signalling: LVSTL at a V_DDQ of 0.5 V, with a 0.3 V option when termination is off. A 1 pulls up to V_DDQ·RTT/(Ron + RTT); with 40 Ω for both, the model’s choice, that is 250 mV, and every receiver decision on the bus is made inside that quarter of a volt.

What LPDDR6 adds is dynamic write NT-ODT: a non-target die on a shared data bus can change its termination during a write, as DDR5’s non-target DRAMs do. It matters wherever more than one die shares the same data lines, as in multi-die packages built for capacity.

Power, and the power network

Dynamic efficiency mode · half the bandwidth on half the I/O

The core supply splits in two, and JEDEC makes both mandatory: V_DD2C at 1.0 V and V_DD2D at 0.875 V, against LPDDR5X’s 1.05 V and 0.9 V. Dynamic voltage and frequency scaling for low power (DVFSL) lowers V_DD2 further at low speeds. For the board, two V_DD2 rails mean two power nets to deliver and decouple where there was one, each with its own target impedance; for the signals, a lower core supply means less margin inside the DRAM for the same noise.

LPDDR6 vs LPDDR5X vs LPDDR5: what changed

In bandwidth, a 24-bit channel at 10.667 Gb/s moves 32.0 GB/s on the wire, of which 28.4 GB/s is data once the 32 extra bits in every 288 are set aside; at 14.4 Gb/s, 38.4 GB/s of data. A 16-bit LPDDR5X channel at 8533 MT/s moves 17.1 GB/s. The LPDDR5X page covers what both generations share: source-synchronous timing, training, and a budget spent on crosstalk and switching noise rather than loss.

What it takes to sign off

At 69 to 94 ps a bit, LPDDR6 is a trained, equalised interface. IP vendors describe receive DFE and termination tuning in their PHYs, and show trained eyes at the starting rate. The board’s part is the familiar LPDDR list, made harder: twenty-four data pins a channel escaping a fine-pitch package, all switching together, now with less time per bit and the same quarter-volt swing. Crosstalk and simultaneous switching noise were already the dominant terms on LPDDR5X, and wider buses give each victim the same neighbours with less time between their edges.

The command bus joins the list. At 5.3 Gb/s per pin it is a high-speed bus with only four wires, and a fault on any of them is a wrong command, which is why it is trained, terminated and, if the system wants, protected by parity.

Go deeper — the PAM4 arithmetic, the road model, and the energy of a 1

A third of the swing. With N levels evenly spaced across a swing V, the gap between adjacent levels is V/(N−1): V for NRZ, V/3 for PAM4. In decibels that is 20·log₁₀(3), or 9.54 dB. In return PAM4 halves the symbol rate for the same bit rate, so its Nyquist frequency halves and so does the loss it sees, roughly. On a channel whose loss at Nyquist is tens of decibels that trade can win; on one with a few, it cannot.

The three roads. The target is 24 pins at the chosen LPDDR6 rate. Faster NRZ carries it on 16 pins, so each runs at 24/16 of the rate: 16 Gb/s for the starting bin. PAM4 carries it on 16 pins at half that, 8 GBd. The wide road runs 24 pins at the bin rate itself, or fewer or more if you change its pins. Every road sees the same physical loss law, 35% skin and 65% dielectric scaled to the loss you set at 5 GHz, evaluated at its own Nyquist frequency, and the same echo at the same delay in picoseconds. The eye is built by superposing the single-symbol response over a PRBS-11 pattern, and the opening is measured, not drawn.

The allowance. Noise and jitter are not simulated bit by bit; they are taken off as ±7 standard deviations, the margin for a bit error ratio of about 10⁻¹². That is a model choice, and a fair one for comparing roads, since all three pay it.

The energy of a 1. A 1 drives current V_DDQ/(Ron + RTT) from the supply for one bit time, so it costs V_DDQ²/(Ron + RTT)·UI: 0.25/80 W for 93.75 ps, about 0.29 pJ. A 0 costs nothing in the termination. This leaves out the energy to charge the line and pins on each transition, which DBI does not reduce in the same way.

What both panels leave out. Crosstalk is in the noise figure, not modelled from neighbours. The driver and termination are 40 Ω each, a model choice; the standard’s values have not been read. The packet panel draws the burst by what it carries, not where each bit travels: the standard defines which pin and beat each bit uses, and the panel does not claim to.

In the real world

LPDDR6 moves to more places than phones. The same standard is pitched at laptops, edge AI boxes, cars and some servers, where LPDDR’s power advantage now competes with DDR5’s capacity. The DDR5 page sets out that trade for LPDDR5X; it applies to LPDDR6 with more bandwidth on the LPDDR side.

Expect the first parts at the starting rate. Announced LPDDR6 DRAMs run at about 10.7 Gb/s. The higher bins depend on DRAMs, PHYs and channels that reach them, and a design should be signed off at the bin it will run, not the top of the standard.

Pins and supplies grow even as bandwidth per pin barely does. Twenty-four data pins a channel and two V_DD2 rails mean more balls, more routing and more decoupling than an LPDDR5X design of the same capacity. That is the price of keeping NRZ, and it is paid on the board.

Where the numbers come from

• JEDEC’s JESD209-6 announcement (July 2025) — the sub-channels, command pins, NT-ODT, supplies, efficiency modes and reliability features. The standard itself has not been read.
• Samsung, “LPDDR6 Key Architecture”, JEDEC LPDDR6 workshop (April 2025) — the comparison with LPDDR5 and LPDDR5X, clocks, voltages, the packet, and the case for wide NRZ.
• Synopsys, “LPDDR6: A Deep Dive Into the JEDEC Press Release” (JEDEC forum, May 2024, before the standard was final), and Synopsys and Cadence product material (2025–2026) — data rates, DBI, ALERT and PHY equalisation.
• SK hynix (March 2026) — the first LPDDR6 DRAM announcement.

Related

• LPDDR5/5X Signal Integrity: WCK, ODT and Training — what LPDDR6 inherits
• DDR5 Signal Integrity: Fly-by, ODT, DFE and Training — the socketed alternative
• NRZ vs PAM4 Signaling: Bandwidth and SNR Trade-off — the level arithmetic, at serial-link scale
• Simultaneous Switching Noise and Ground Bounce — what a wide bus switching together does
• PCB Crosstalk: NEXT, FEXT, and Mutual Coupling — the dominant LPDDR impairment