SIPI

Labs / 03

Lab C: PDN Impedance and Transient Droop

By Geetansh Arora — Principal SI/PI Engineer14 min

A power delivery network passes current through different paths as frequency changes. Impedance peaks often appear near the handover between paths, where one capacitor bank has become inductive while the next is still capacitive. This lab connects those frequency responses to branch current, transient droop, and the different effects of die and board loads.

Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.

One ladder · regulator to die numerical worst peak — over target — at — |Z| there — phase — combined die droop — overshoot — transient method — load knee —
—
Impedance the die sees
at the dieseen at the boardseen at the VRMtarget
The ladder, at the selected frequency
Droop — load applied, then released
Which bank supplies the current
Phase — who is winning
Die-load current spectrum (load 1)

Two loads: how board and die activity share a rail

Voltage response
Load-current timing

Learning sequence and notes

Load 1 draws current at the die; load 2 draws at the board node. Try enabling load 2, then move its start time. The same current change can produce different voltage excursions at the two observation points. This ladder has one die and one board load.

Solid: die current. Dashed: board current. Positive current is drawn from the rail; negative voltage is droop. Start times and pulse widths are in physical time. Width runs from the start of the rising edge to the start of the falling edge; both edges use the selected duration.

The transient starts from rest and follows the load changes forward in time. Extending the record reveals later behavior without changing earlier samples. A finite timestep still limits resolution. Droop and overshoot are measured until the rail settles, which with a slow regulator can be long after the plotted window; the readout then gives the time of the peak. A quiet baseline is expected here; it does not prove timestep convergence.

The frequency and branch-current panels above use a unit excitation at the die. Their peak selection also sets the transfer-impedance readout here. A peak identifies a possible ringing mode; the load spectrum and timing determine how strongly it is excited. The original droop panel shows the combined die response. A single target impedance times one load current does not bound two transfer paths, so its target line is hidden while the board load is active.

Predict

Keep load 1 unchanged and enable the board load. Will equal current changes create equal voltage excursions at the die, or will the shared paths and injection locations matter?

Experiment

Start from Typical SoC rail, set the board load to 3 A, and compare load 1 alone, load 2 alone, and both combined. Then move the board-load start time. Starts and widths are in ns; edges are in ps.

Explain

The die and board injections reach each observation through different complex transfer impedances. Their signed time responses add. Adding separate worst-droop values would discard timing and phase.

Transfer

Can equal and opposite current changes cancel at every node?

Check your reasoningAt one common injection node they cancel in this linear model. At distinct nodes they generally do not, because the transfer paths differ.

Transfer impedance: which load affects which node?

Notes

Matching observation and excitation nodes gives driving-point impedance. Different nodes give transfer impedance: the voltage at one node per amp applied at the other. This passive reciprocal circuit has equal forward and reverse transfer impedances, although the two driving-point impedances can differ. Keep the circuit fixed and compare all four selections.

The plot shows transfer magnitude with common bounds across all four node pairs. Entering Hz, clicking the plot, or using its left/right arrow keys selects the nearest computed sample; the readout gives its actual frequency, complex impedance, and principal phase. There is no separate phase curve. Frequency selection also moves the markers in the original unit die-excitation investigation, whose branch-current shares keep that excitation. No scalar target line is applied here. Exports preserve real and imaginary impedance in ohms.

In circuit schematics, a DC power rail is drawn as a flat horizontal line connecting a voltage regulator module (VRM) to a processor, surrounded by dozens of decoupling capacitors. The intuitive mental model is that capacitors act as a static “reservoir” or bucket of charge: when the processor demands a sudden spike of current, charge drains from the bucket, and as long as the total capacitance is large enough, the voltage rail remains stable.

In high-speed digital systems, the reservoir picture leaves out how fast the charge can arrive. Loop inductance (L) opposes rapid changes in current (V = L · di/dt), so what matters is not only how much charge each stage holds but how much inductance stands between it and the load. Measured that way, the VRM is furthest from the die, then the bulk capacitors, then the board ceramics, with on-die capacitance right at the transistors.

The power distribution network is therefore not a reservoir; it is a high-speed relay race across frequency. Each stage of the network is only fast enough to supply current within a specific frequency window. This interactive lab lets you configure each runner in the relay — VRM bandwidth, bulk capacitors, board MLCCs, package inductance, and on-die capacitance — to see how their handover creates the board's composite impedance profile and transient droop.

A relay race, not a reservoir

A bucket-of-charge picture can help at low frequency, but it leaves out the delivery path that matters as frequency rises. We also need to ask how quickly current can reach the load; the inductance in that path sets this limit alongside the capacitance.

So the network becomes a relay. The regulator supplies everything up to its loop bandwidth. Bulk capacitors take over into the hundreds of kilohertz. Board capacitors carry the megahertz range until their mounting inductance stops them. The package handles tens of megahertz, and above roughly a hundred megahertz nothing outside the die can reach the load in time at all.

fSRF = 1 / (2π √(L·C)) below it a capacitor; above it an inductor; nothing else to remember

Every peak is a failed handover

Between any two banks there is a band where the upstream one has passed its resonance and become an inductor, while the downstream one is still below its own resonance and still a capacitor. An inductor in parallel with a capacitor is a parallel resonance, and a parallel resonance is a maximum of impedance, not a minimum.

That is the entire mechanism behind every peak on the impedance panel, and it explains the result that surprises people most: adding capacitance moves a peak rather than removing it. The height of a peak is set by how much resistance is in the loop. The only three levers are damping it, moving it somewhere the load has no energy, or reducing the inductance that created it.

Every peak is a handover · each stage’s own impedance, and the whole
1 mΩ 10 mΩ 100 mΩ 1 Ω 1 kHz 100 kHz 10 MHz 1 GHz regulator → bulk bulk → board board → die regulator bulk board bank on-die C package L bold: |Z| at the die, all of it together
The network is low only where some stage is low, and every peak sits where one stage hands the load to the next. The thin curves are each stage on its own: the regulator, whose impedance climbs past its loop bandwidth; the bulk and board banks, each a V with its bottom at its own resonance; the on-die capacitance, falling with frequency; and the package inductance (dashed), which the die has to look through to reach the board. The bold curve is what the die sees with all of them connected. Between two stages there is a band where the upstream one has already turned inductive and the downstream one is still a capacitor, and that pair is a parallel resonance: a peak. The tallest here is the last handover, where the package inductance meets the on-die capacitance, because nothing outside the die is fast enough to help there. Illustrative values chosen to put each stage in the band the page describes, with no package capacitors, so four stages and three handovers.
Go deeper — target impedance, and what this model leaves out

The target impedance line is the crudest useful specification in power integrity:

Ztarget = ΔVallowed / ΔImax one number, applied across every frequency the load excites

It is crude because it assumes the load draws current at every frequency equally, which no real load does — that is exactly why the current spectrum panel is on this page and on its own axis. A peak that sits where the load has almost no spectral content costs nothing; a smaller peak sitting on a clock harmonic can dominate the noise. Comparing the two panels is worth more than either alone.

What the model leaves out:

  • Plane cavity modes. This is a lumped ladder, so the planes are single inductances. A real plane pair is a resonant cavity with modes of its own — see plane resonance.
  • Spatial distribution. Every capacitor in a bank is at the same place here. In reality a capacitor two inches away has more loop inductance than one beside the pin and belongs in a different bank.
  • The VRM control loop. Modelled as a resistance rising into an inductance, which is the right shape but not a real compensator — see VRM loop bandwidth.
  • Linear only. The loads draw the current you set whatever the rail does, and the regulator never runs out of headroom. That describes a rail moving by tens or hundreds of millivolts well. It does not describe one moving by volts, which the current and edge controls can produce, so above half a volt at either node the readout says the result is beyond the model: far over budget, not a voltage a real rail of about a volt would reach.
  • The transient window. The causal calculation starts from zero incremental state. Extending the record reveals later behavior without changing earlier samples. Refining the timestep checks resolution; it is a separate question from whether the baseline is quiet. Droop and overshoot are measured through the record and then through the rail’s ring-down after the loads turn off, until it settles, so a slow regulator’s late overshoot is not missed.

In the real world

The practical sequence is almost always: get the impedance curve, find the worst peak, then ask which two banks made it — that is what the topology panel is for. Only then does a fix make sense, because the fix depends entirely on the answer. A peak between the board and package banks is a mounting-inductance problem. A peak between bulk and board is usually a damping problem.

The final check connects the impedance to the actual load spectrum, timing, and location. A target exceedance where the load has little spectral energy may have a small transient effect, while a resonance aligned with significant activity may need attention even when a scalar driving-point target appears satisfactory. Use the two-load view to examine the relevant transfer paths before drawing that conclusion.

Where this is explained

This page is the instrument. The mechanisms it lets you change are described on the topic pages below, each one linked for the specific thing it explains rather than as a general reading list.