Signal Integrity Interview Questions and Answers

Short answer. Making sure a signal arrives at the receiver with enough voltage and timing margin to be read correctly, at the error rate the system needs. It covers what the interconnect does to a signal on the way: reflections, loss, crosstalk, noise and jitter.

A strong answer adds. Signal integrity starts to matter when the interconnect is no longer a short wire: when its delay is comparable to the signal’s edge, so voltage and current travel as waves. From then on the board, package and connectors are part of the circuit, and their design is about controlling impedance, loss and coupling.

Likely follow-up: When does a trace stop being a plain wire? When its round-trip delay is a meaningful fraction of the rise time.

Read: When Is a Trace a Transmission Line? Critical Length · Rise Time and Bandwidth: Edge Rate, Not Clock Rate

Short answer. Because a signal’s spectrum is set by how fast it changes, not how often it repeats. A 100 ps edge has significant energy up to about 0.5/t_r = 5 GHz, whether the clock repeats at 100 MHz or at 10 MHz.

A strong answer adds. The knee, 0.5/t_r, is where the spectrum of a trapezoidal edge starts to fall away steeply; the −3 dB bandwidth of a single-pole edge is 0.35/t_r, 3.5 GHz here. The clock rate only sets how closely the harmonics are spaced beneath that envelope: for a 100 MHz clock the 50th harmonic sits at the knee. Reflections, crosstalk and loss all respond to the edge, so a ringing slow clock is more often cured by a slower edge than by a lower frequency.

Likely follow-up: Then why quote Nyquist for a data link? For random data the fastest repeating pattern, 1010…, has a period of two bits, so the channel’s loss is judged at half the bit rate. The edge decides how much energy lies above that frequency.

Read: Rise Time and Bandwidth: Edge Rate, Not Clock Rate · Bit Rate, UI and Nyquist Frequency Calculator
Try it: the spectrum panel: move the clock rate, then the rise time

Short answer. The ratio of voltage to current for a wave travelling along a line, Z₀ = √(L/C) per unit length. It is not a resistance you can measure with an ohmmeter; it is what the line looks like to an edge before any reflection comes back.

A strong answer adds. Geometry and material set it: a wider trace or a thinner dielectric adds capacitance and lowers Z₀; a higher D_k lowers it too. A stripline is surrounded by dielectric, a microstrip is partly in air, so for the same impedance they need different widths, and the microstrip is faster.

Likely follow-up: Why 50 Ω? Largely a historical compromise in coaxial cable between low loss and power handling, which became the standard for test equipment; many PCB nets use other values, such as 85 or 100 Ω differential.

Read: Characteristic Impedance (Z0) of PCB Transmission Lines · Microstrip and Stripline Impedance Calculator
Try it: the line impedance calculator

Short answer. When its round-trip delay is a significant fraction of the signal’s rise time. A common form of the rule is 2T_d > t_r/3, which gives a critical length of t_r/(6·t_pd).

A strong answer adds. The rule is about the edge, not the clock frequency, and it is a boundary of degree: below it reflections are absorbed into the edge, above it they appear as overshoot and ringing. For a 100 ps edge on stripline the critical length is only a few millimetres, so almost every high-speed net qualifies.

Likely follow-up: So does a 10 MHz clock need termination? If its driver has a fast edge and the trace is long, yes: the edge, not the 10 MHz, decides.

Read: When Is a Trace a Transmission Line? Critical Length · Electrical Length and Critical Length Calculator
Try it: the critical-length panel

Short answer. Part of it reflects. The reflection coefficient is Γ = (Z_L − Z₀)/(Z_L + Z₀): +1 for an open, −1 for a short, 0 for a matched load. The rest is transmitted, 1 + Γ times the incident voltage.

A strong answer adds. The reflection travels back to the source, where it reflects again by the source’s own Γ. The result is a sequence of steps that settles to the DC value: ringing when the two coefficients have opposite signs, a staircase when they have the same sign. A short discontinuity, such as a via, behaves as a lumped capacitance or inductance instead of a step.

Likely follow-up: Why does an open end double the voltage? The forward and reflected waves add in voltage and cancel in current, which is what an open requires.

Read: Transmission-Line Reflections and Ringing · TDR (Time-Domain Reflectometry): Reading PCB Impedance
Try it: the travelling-waves lab, with an open load

Short answer. Series termination puts a resistor at the driver so that driver plus resistor equals Z₀; it suits point-to-point nets and costs no DC power. Parallel termination puts Z₀ at the receiver, where it absorbs the wave on arrival; it suits a multi-drop bus, at the cost of DC current.

A strong answer adds. A bidirectional net needs termination at whichever end is receiving, which is why memory interfaces switch on-die termination with the direction of transfer. Series termination launches a half-amplitude wave that doubles at the open far end, so only the end of the line sees a clean full swing; loads along the line see a step. Parallel termination gives a full swing everywhere after one flight but burns power, which is why Thevenin, AC and on-die termination exist. Most modern interfaces terminate on die and switch it in only when needed.

Likely follow-up: Why is the far end of a series-terminated line clean but the middle is not? The middle sees the half-amplitude launched wave first, then the reflection from the open end.

Read: Termination Schemes: Series, Parallel, Thevenin and AC · Transmission-Line Reflections and Ringing

Short answer. A branching (T) topology gives every stub its own reflection, and the stubs add up as the speed rises. A fly-by chain runs one line past every device with very short stubs and terminates once, at the end, so the reflections stay small and regular.

A strong answer adds. The cost is arrival time: the signal reaches the first and the last device at different moments, so each device sees clock and data skewed by a different amount. DDR3 introduced write leveling for this, in which the controller measures each device’s skew and delays its data to match. Every DRAM’s input capacitance also loads the line, which lowers its effective impedance and slows it, so stub length and load capacitance are what you control. DDR5 keeps a fly-by for commands on the module and a short point-to-point path for data.

Likely follow-up: Why not use fly-by for the data as well? Each data bit only has to reach one device, so a dedicated point-to-point wire is cleaner than any chain, and there is no skew to level.

Read: DDR5 Signal Integrity: Fly-by, ODT, DFE and Training · Termination Schemes: Series, Parallel, Thevenin and AC
Try it: the fly-by lab on the DDR5 page, with write leveling off and then on

Short answer. At high frequency it flows in the reference plane directly under the trace, because that path has the least inductance. At a split it has to detour around the gap, which adds inductance, creates a discontinuity and couples the signal into everything sharing the detour.

A strong answer adds. The detour shows up as a bump on a TDR, as crosstalk between nets that share the gap, and as radiation. The same thing happens at a layer change when the reference plane changes and there is no nearby return via or capacitor between the two planes. The fixes are routing over a continuous plane, stitching vias beside signal vias, and keeping antipads from merging into slots.

Likely follow-up: Does a differential pair need a return path? Its odd mode mostly returns through the partner trace, but common-mode current from any imbalance still needs the plane.

Read: Return Current Paths: Reference Planes, Splits and Gaps · Stitching Vias and PCB Layer Transitions · High-Speed Vias: Stubs, Resonance, and Backdrilling

Short answer. Conductor loss and dielectric loss. Conductor loss grows as the square root of frequency because the skin effect crowds current to the surface; dielectric loss grows linearly with frequency and the loss tangent. Above a few gigahertz on typical laminates, dielectric loss usually dominates.

A strong answer adds. Copper roughness adds to conductor loss once the skin depth becomes comparable to the roughness, and glass weave changes the effective D_k along a trace. The levers are a lower-loss laminate, smoother copper, wider traces and shorter routes. Loss is not a problem in itself; the frequency dependence is, because it smears edges into ISI.

Likely follow-up: What is the skin depth of copper at 1 GHz? About 2 µm.

Read: PCB Trace Loss: Skin Effect, Dielectric Loss, Roughness · Skin Depth and Surface Roughness Calculator · PCB Channel Loss Budget Calculator
Try it: the loss panel, sweeping the loss tangent

Short answer. Energy from one bit spilling into the bits around it. A lossy or reflective channel spreads a single bit’s pulse over several unit intervals, so each sample contains a little of its neighbours.

A strong answer adds. The single-bit, or pulse, response shows it directly: the main cursor at the sampling point, pre-cursors before it and post-cursors after. Loss produces a long, smooth tail; reflections produce discrete echoes at later bits. The worst case is the pattern that adds every post- and pre-cursor with the wrong sign, which is what peak-distortion analysis finds.

Likely follow-up: Which patterns are worst for ISI? A long run of one value followed by a single opposite bit, because the tail of the run is largest just as the isolated bit needs to stand out.

Read: Intersymbol Interference (ISI) and Channel Memory · Eye Closure Causes: Loss, Reflections and Crosstalk
Try it: the ISI panel

Short answer. It overlays every bit on one unit interval, so the open area in the middle is the voltage and timing margin left after ISI, noise and jitter for the bits you simulated or captured. Eye height and eye width are its two dimensions.

A strong answer adds. An eye from a few thousand bits says little about rare events at 10⁻¹²; for that you need jitter and noise decomposed and extrapolated, or a statistical simulation. An eye also depends on where it is taken: at the pin, after the package, or after equalisation at the slicer. A compliance eye uses a mask, which is a statement about the receiver, not about the channel.

Likely follow-up: The eye is open in simulation but the link fails. Why? Missing crosstalk, supply noise, a model that does not match the hardware, or simply too few bits.

Read: Eye Diagram: How to Read Eye Height and Eye Width · Statistical vs Bit-by-Bit Channel Simulation · Transmitter Compliance Masks and Receiver Eye Masks

Short answer. Random jitter is unbounded and Gaussian, so it is described by its rms. Deterministic jitter is bounded: data-dependent jitter from ISI, duty-cycle distortion, periodic jitter and crosstalk. Total jitter at a BER is deterministic jitter plus 2Q(BER) times the random rms, about 14 sigma at 10⁻¹².

A strong answer adds. Because random jitter has no peak value, the total grows as you ask for a lower BER, which is why a jitter number without a BER is meaningless. The dual-Dirac model that splits jitter this way is a fit to the tails, not a measurement, and it can mislead on links with unusual jitter.

Likely follow-up: Can you measure 10⁻¹² directly? At a few gigabits per second it takes minutes per sampling point; the bathtub is extrapolated from a shorter capture.

Read: Jitter Components: RJ, DJ, DCD, PJ, and TJ · Bathtub Curves and BER Extrapolation · BER, Q-Factor and Total Jitter Calculator

Short answer. Compare the time the data is valid at the receiver with the time the receiver needs. The valid time is the unit interval minus the skew, jitter and pattern-dependent spread between the data and its strobe; the receiver’s setup and hold window has to fit inside what is left.

A strong answer adds. Lay the terms out one by one. Static skew comes from length and layer mismatch: 1 mm of stripline is 6.7 ps, so 10 mm is 67 ps, 43% of the 156 ps unit interval of a 6400 MT/s bus. Microstrip is faster, about 5.8 ps/mm, so a net routed partly on each layer must be matched in delay, not in length. Jitter, ISI and crosstalk-induced delay variation come next; layout cannot remove them, and training removes static skew but not noise. What remains is the margin, and it has to be quoted at a BER or a mask, not as one number.

Likely follow-up: Why does the same length mismatch hurt more at a higher data rate? The skew in picoseconds does not change while the unit interval shrinks: 67 ps is about 21% of the 312.5 ps interval at 3200 MT/s but 43% of it at 6400 MT/s.

Read: Channel Loss Budgeting Across Die, Package, and Board · DDR5 Signal Integrity: Fly-by, ODT, DFE and Training · Reporting Signal and Power Integrity Margin

Short answer. Near-end crosstalk appears at the end of the victim nearest the aggressor’s driver and saturates once the coupled section’s delay exceeds about half the rise time. Far-end crosstalk appears at the far end, travels with the aggressor’s edge and grows with coupled length.

A strong answer adds. Both come from mutual capacitance and mutual inductance. They add at the near end and subtract at the far end, so in a homogeneous dielectric such as stripline far-end crosstalk nearly cancels, while a microstrip, partly in air, generally has noticeable far-end crosstalk because its capacitive and inductive coupling no longer cancel. Far-end crosstalk is also proportional to the edge rate, so faster edges make it worse.

Likely follow-up: How do you reduce it? More spacing, a closer reference plane, stripline instead of microstrip, shorter parallel runs, slower edges where allowed, and keeping return paths continuous.

Read: PCB Crosstalk: NEXT, FEXT, and Mutual Coupling · Capacitive vs Inductive Coupling: dV/dt and dI/dt Noise
Try it: the crosstalk panel, changing the coupled length

Short answer. A layout guideline: keep two traces at least three trace widths apart, centre to centre, so that much less of one trace’s field reaches the other. It is a sound starting point for crosstalk, not a result derived for your stackup.

A strong answer adds. The physics sets spacing relative to the height above the reference plane, not to the trace width: an aggressor’s field terminates on the plane beneath it, so a closer plane often cuts coupling more cheaply than space does. Beyond about five widths more spacing buys very little. A rule that ignores the layer height will be too tight in one stackup and too loose in another, so check long parallel runs between fast edges against a crosstalk budget, with a coupled-line model or a field solver.

Likely follow-up: Is 3W enough between a clock and a data line? Not by itself. Judge it by the noise it can add against the receiver’s margin, and give a clock or another sensitive net more room, a shorter parallel run, or both.

Read: PCB Crosstalk: NEXT, FEXT, and Mutual Coupling · Capacitive vs Inductive Coupling: dV/dt and dI/dt Noise · PCB Stackup Design and Dielectric Selection
Try it: the crosstalk panel, whose controls are the coupling ratios that spacing and height set

Short answer. The receiver looks at the difference between two lines, so noise common to both cancels, the swing on each line can be smaller, and the two return currents mostly cancel. Differential impedance is the impedance the pair presents to an odd-mode signal: twice the odd-mode impedance of one line.

A strong answer adds. Coupling between the two lines lowers the odd-mode impedance and raises the even-mode impedance, so a pair designed for 100 Ω differential is not two independent 50 Ω lines. Any asymmetry, such as length skew, unequal coupling to neighbours or glass weave, converts some differential signal into common mode, which is what radiates and what a receiver may not reject.

Likely follow-up: Does length matching within a pair matter? Yes: intra-pair skew is mode conversion. Matching between pairs matters only as much as the protocol’s skew budget.

Read: Differential Signaling: Common Mode and Mode Conversion

Short answer. S21 is the fraction of a wave that gets through, insertion loss; S11 is the fraction reflected back, return loss. In mixed-mode form, SDD21 is the differential insertion loss and SCD21 is how much differential signal turns into common mode on the way, which is mode conversion.

A strong answer adds. S-parameters are measured or simulated against a reference impedance at defined ports; change the reference and they change. They must be passive (no gain at any frequency) and causal (no response before the input), and a model that breaks either produces eyes that are too good or simulations that do not converge.

Likely follow-up: Why is my S-parameter model non-causal? Usually truncated bandwidth, poor interpolation, or a dielectric model whose loss and phase are not consistent.

Read: S-Parameters Explained: S11, S21 and Mixed-Mode · Time vs Frequency Domain: Impulse, Step, Convolution
Try it: the S-parameter panel

Short answer. At common-mode current. Radiation comes mostly from current that flows the same way on both conductors, and the eye only looks at the difference, so a pair can be clean differentially and still be converting some of its signal to common mode.

A strong answer adds. Conversion comes from asymmetry: skew inside the pair, a via or stub on only one line, a glass-weave difference, unequal coupling to a neighbour or a plane edge, or an imbalanced driver. It appears in S-parameters as SCD21, differential in and common mode out. The first fix is symmetry at the source of the mismatch, together with a continuous return path; filters, common-mode chokes and shields treat the symptom, and are worth having once the conversion is as small as the layout allows.

Likely follow-up: Why does a cable make it worse? It is a long, efficient antenna attached to the board’s reference, so a small common-mode voltage drives a useful amount of current into it.

Read: Differential Signaling: Common Mode and Mode Conversion · S-Parameters Explained: S11, S21 and Mixed-Mode · Return Current Paths: Reference Planes, Splits and Gaps

Short answer. A CTLE is an analogue high-pass that boosts high frequencies to undo channel loss, but it boosts noise and crosstalk with them. An FFE at the transmitter pre-distorts the signal, at the cost of launched swing. A DFE at the receiver subtracts post-cursor ISI using the bits it has already decided, without amplifying noise.

A strong answer adds. An FFE is typically de-emphasis, often with a pre-cursor tap. They are complementary: the CTLE and FFE shape the pulse, the DFE cancels what remains after the cursor. A DFE cannot touch pre-cursor ISI, only reaches as many bits as it has taps, and a wrong decision feeds back into the next one. Adaptation chooses the settings during link training.

Likely follow-up: Why not use only a DFE? It cannot remove pre-cursor ISI, and with a heavily lossy channel the first decision is already unreliable.

Read: SerDes Equalization: CTLE, FFE, DFE and CDR · Eye Closure Causes: Loss, Reflections and Crosstalk
Try it: the equaliser panel

Short answer. A CDR recovers a sampling clock from the data transitions, so a serial link needs no separate clock. Jitter transfer is how much input jitter the recovered clock follows; jitter tolerance is how much input jitter, at each frequency, the receiver can take before errors rise.

A strong answer adds. The loop tracks slow jitter, below its bandwidth, so that jitter does not close the eye; fast jitter passes through untracked and spends margin. Peaking in the loop amplifies jitter near its natural frequency. Spread-spectrum clocking works only because its modulation is slow enough for the CDR to follow.

Likely follow-up: What sets the loop bandwidth? A trade between tracking low-frequency jitter and filtering high-frequency noise, usually defined by the protocol.

Read: CDR, Jitter Transfer and Jitter Tolerance (JTOL) · Jitter Components: RJ, DJ, DCD, PJ, and TJ

Short answer. PAM4 sends two bits per symbol, so the symbol rate and the Nyquist frequency halve for the same bit rate, and the channel loss at Nyquist drops. The cost is that three eyes share the same swing, each a third of the height, about 9.5 dB less.

A strong answer adds. The receiver needs three slicers instead of one. It pays when loss at Nyquist is large enough that halving the frequency saves more than 9.5 dB, as in long backplanes and PCIe 6.0. On a short, noisy channel it does not, which is why LPDDR6 went to wider NRZ instead. PAM4 links usually rely on forward error correction because their raw error rate is higher.

Likely follow-up: Why is the PAM4 eye width smaller too? Transitions between non-adjacent levels cross the thresholds at different times, and the eyes are shorter, so timing margin shrinks as well.

Read: NRZ vs PAM4 Signaling: Bandwidth and SNR Trade-off · LPDDR6 Signal Integrity: Wide NRZ and Sub-Channels · PCIe 6.0 Signal Integrity: PAM4, FLIT, and FEC
Try it: the three-roads panel on the LPDDR6 page

Short answer. A via is a short vertical discontinuity: its barrel and pads add capacitance, its return path adds inductance, and the unused length below the signal layer is a stub. An open stub resonates at the frequency where it is a quarter wavelength long and notches the channel there.

A strong answer adds. The notch frequency is c/(4·L·√D_k), so a 60 mil stub notches near 25 GHz. Backdrilling, blind vias or routing on the layer that leaves the shortest stub move the notch out of band. Return vias next to signal vias keep the return path short when the reference plane changes.

Likely follow-up: Where should you route a high-speed signal to minimise the stub? On the layer furthest from the component side the via enters from, unless the via is backdrilled.

Read: High-Speed Vias: Stubs, Resonance, and Backdrilling · Via Stub Resonance Calculator · Stitching Vias and PCB Layer Transitions

Short answer. Every high-speed signal layer next to a continuous reference plane, power and ground planes paired closely for low inductance and plane capacitance, a symmetric build to avoid warp, and a laminate chosen for the loss budget at the fastest interface’s Nyquist frequency.

A strong answer adds. Then trace widths for the target impedances on each layer, including tolerance; which interfaces go on which layers to keep via stubs short; where the planes split for different supplies, and making sure no fast signal crosses a split. Doing this early is cheaper than any fix later.

Likely follow-up: Microstrip or stripline? Stripline for crosstalk and shielding; microstrip is faster and avoids vias, but has far-end crosstalk and is exposed.

Read: PCB Stackup Design and Dielectric Selection · PCB Impedance Tolerance: Etch, Glass Weave, Stackup · BGA Escape Routing and Breakout Congestion

Short answer. Laminate is woven glass in resin, and the two have different dielectric constants. A trace running along the weave can sit over glass while its partner sits over resin, so the two signals travel at different speeds even when their lengths are equal.

A strong answer adds. The result is a delay difference inside the pair, which becomes mode conversion and a differential eye with less margin. It cannot be matched out by length, because it changes along the trace with where the weave happens to be. The fixes are upstream of layout: route at a small angle to the weave so each line averages over glass and resin, or specify a spread or mechanically flattened glass style. How much it matters depends on the data rate and the length of the run.

Likely follow-up: Does it matter on a 1 Gb/s link? Rarely. It matters at the rates where the unit interval is short enough that tens of picoseconds are a large fraction of it.

Read: PCB Impedance Tolerance: Etch, Glass Weave, Stackup · Differential Signaling: Common Mode and Mode Conversion · PCB Stackup Design and Dielectric Selection

Short answer. They block DC, so that transmitter and receiver can each use their own common-mode level and survive different supply domains and hot-plugging. A small ceramic capacitor goes in series with each line of the pair, in the place the interface specification gives, often at the transmitter end.

A strong answer adds. The capacitor and the receiver’s termination form a high-pass filter: 100 nF into 50 Ω per line has its corner near 32 kHz. A run of 128 identical bits at 10 Gb/s lasts 12.8 ns, about 0.26% of the 5 µs time constant, so the line barely droops. The trouble is the footprint, not the value: a pad wider than the trace is extra capacitance over the plane, a dip on a TDR. Use a small package, a cut-out in the plane beneath the pads, and an identical, symmetrical placement on both lines of the pair so that the mismatch does not convert modes. Keep vias away from the pads and the capacitor off any stub.

Likely follow-up: What goes wrong if the capacitor is too small? The corner rises, long runs of identical bits droop, and the baseline wanders with the data, which closes the eye in the way ISI does.

Read: TDR (Time-Domain Reflectometry): Reading PCB Impedance · Differential Signaling: Common Mode and Mode Conversion · Stitching Vias and PCB Layer Transitions

Short answer. A TDR sends a fast step and plots the reflection against round-trip time, so time is distance and height is impedance. A dip is capacitance, a bump is inductance, and a step is a section at a different impedance.

A strong answer adds. The end of the line reads +1 for an open and −1 for a short. Two features closer than about half the rise distance merge into one, a short feature never reaches its true impedance, loss makes a uniform line read as rising, and everything behind a large mismatch is seen through it. The area of a lumped dip gives its capacitance whatever the edge.

Likely follow-up: How do you get a TDR from a VNA? By inverse Fourier transform of S11; the measurement bandwidth and the window set the effective rise time.

Read: TDR (Time-Domain Reflectometry): Reading PCB Impedance · SI/PI Measurement: Probes, Fixtures and Calibration
Try it: the TDR lab

Short answer. A VNA measures the channel itself in the frequency domain, as S-parameters, with high dynamic range: insertion loss, return loss, crosstalk, resonances. An oscilloscope measures the signal in the time domain: the eye, jitter and noise with the real driver and receiver.

A strong answer adds. Both need de-embedding of fixtures and probes to the reference plane you care about, and probing itself loads the circuit. A VNA answers “what is this interconnect?”; a scope answers “what is the signal doing?”. Correlation is comparing each against the simulation that predicted it.

Likely follow-up: Why does a probe change the measurement? Its tip capacitance and ground lead inductance form a resonance, and its loading adds to the node.

Read: SI/PI Measurement: Probes, Fixtures and Calibration · S-Parameter De-Embedding and Fixture Removal · Simulation-to-Measurement Correlation for SI/PI

Short answer. IBIS describes a buffer’s analogue behaviour; AMI adds executable models of the transmitter and receiver equalisation and clock recovery, so a channel simulator can run millions of bits with realistic adaptation. A transistor-level model is accurate but far too slow for that.

A strong answer adds. AMI models can be statistical, which is fast and assumes a linear, time-invariant channel, or time-domain, which handles adaptation and nonlinearity bit by bit. The channel itself comes in as S-parameters. The model is only as good as its correlation to silicon, which is why vendors publish correlation reports.

Likely follow-up: Why statistical analysis for 10⁻¹²? Because simulating a trillion bits in the time domain is not practical; statistical methods compute the distribution directly.

Read: IBIS vs IBIS-AMI vs SPICE: Choosing SI Models · Statistical vs Bit-by-Bit Channel Simulation · Signal Integrity Simulation Workflow

Short answer. A capacitive discontinuity: a via, a pad, a component land, a test point. A capacitance pulls the reflection negative while the edge charges it, then the line reads its own impedance again.

A strong answer adds. Its size comes from the area of the dip in ρ·time, which equals Z₀C/2 for any edge: 25 ps of area on a 50 Ω line is 1 pF. In the plot the dip is about 0.43 deep and 53 ps wide at half depth, so depth times width is about 23 ps: close to the true area of 25 ps, which is the 1 pF used to draw it. Its depth depends on the edge as much as on the capacitance, so depth alone is not a measure. A bump instead of a dip would be series inductance, such as a neck or a wire.

Likely follow-up: Two vias close together show as one dip. Why? Their reflections are closer together than the edge; a faster edge separates them.

Read: TDR (Time-Domain Reflectometry): Reading PCB Impedance
Try it: the TDR lab: “A via: the dip” and “Two vias, one dip”

Short answer. Almost always a resonance: an unused via stub a quarter wavelength long at that frequency, or a stub-like structure such as an unterminated branch or a connector pin.

A strong answer adds. Compute the stub length the notch implies and compare it with the stackup: here the notch is at 20 GHz, and a quarter wavelength there in a dielectric of D_k 4 is about 1.9 mm, 74 mil, a plausible stub through a thick board. If it matches a via stub, backdrill it or change layers. If the notch is inside the band the protocol uses, the eye shows it as a reflection-like tail and the equaliser cannot remove it.

Likely follow-up: What would you see in the time domain? A ringing tail on the pulse response at the notch frequency.

Read: Via Stub Resonance Calculator · High-Speed Vias: Stubs, Resonance, and Backdrilling · S-Parameters Explained: S11, S21 and Mixed-Mode

Short answer. ISI from loss: the long run charges the channel’s slow tail, and the single opposite bit afterwards cannot get across the threshold in time. Discrete echoes landing on particular later bits point to reflections instead.

A strong answer adds. In the waveform, the alternating bits cross the threshold with room to spare, while the lone 1 after seven 0s, and the lone 0 after seven 1s, only just make it: the slow part of the response is still charged from the run. Look at the pulse response: a long smooth tail means loss, and the fix is equalisation or a shorter, lower-loss channel; separate bumps at fixed delays mean reflections, and the fix is the discontinuity that causes them. Crosstalk, by contrast, follows what the neighbours are doing, not the victim’s own pattern.

Likely follow-up: How would you confirm it? Change the pattern, or the equalisation, and see which part of the eye moves.

Read: Intersymbol Interference (ISI) and Channel Memory · Eye Closure Causes: Loss, Reflections and Crosstalk · Eye Diagram: How to Read Eye Height and Eye Width
Try it: the channel lab

Short answer. Narrow it down in the order that is cheapest and most informative: confirm the failure and its signature, then compare the hardware with what was simulated, then find which assumption differs.

A strong answer adds. Check the obvious first: the right build, the right settings, training results and margins. Then compare measurement and model in the same domain at the same reference plane: TDR or VNA of the channel against the simulated S-parameters, the eye at a probe point against the simulated eye there. Common culprits are a stackup or material that differs from the model, a missing stub or connector, crosstalk or supply noise that was not in the simulation, or equalisation settings that did not adapt as expected.

Likely follow-up: The error rate changes with temperature. What does that suggest? Loss and timing drift with temperature, so look at margin and retraining, not at a single failure.

Read: SI/PI Debugging: From Symptom to Cause · Simulation-to-Measurement Correlation for SI/PI · SI/PI Measurement: Probes, Fixtures and Calibration

Short answer. Coupling: crosstalk from the neighbour’s traces, or noise through a shared supply or return path, such as simultaneous switching noise moving the reference.

A strong answer adds. Separate the two by changing what the neighbour does: if errors follow its edge timing and coupled length, it is crosstalk; if they follow how many of its bits switch together, it is switching noise through the power or ground network. Look for shared via fields, a gap in the reference plane under both buses, and shared supply pins.

Likely follow-up: How would you prove it on the bench? Correlate error timestamps with the aggressor’s activity, and measure the victim’s noise with the aggressor on and off.

Read: PCB Crosstalk: NEXT, FEXT, and Mutual Coupling · Simultaneous Switching Noise and Ground Bounce · Return Current Paths: Reference Planes, Splits and Gaps · SI/PI Debugging: From Symptom to Cause