Interactive model assumptions and evidence

Target impedance of a rail from voltage, ripple and current step.

Topology

A linear network and a current step with a flat spectrum.

Reference planes

The load's supply pins.

Equations

• Z_target = V*ripple/dI

Units

V, A, ohm

Validity

One ripple figure at all frequencies.

Numerics

Closed form.

Known limitations

A flat target ignores the load's current spectrum; staying under it is sufficient, not necessary.

Evidence

check-models.js — Calculator: target impedance (the step through the target reproduces the ripple budget; scaling).

Compare the round trip against the edge.

Topology

One uniform line.

Reference planes

Both ends.

Equations

• 2*Td > tr/3
• tpd=84.7*sqrt(Dk_eff) ps/in

Units

ps, in

Validity

One driver, one receiver, uniform line, lossless.

Numerics

Exact arithmetic.

Known limitations

One driver, one receiver, uniform line, lossless.

Evidence

check-numbers.py — tpd for stripline and microstrip recomputed.

Show a channel's memory as specific earlier bits.

Topology

Shared channel impulse; cursor and neighbours.

Reference planes

Receiver sampling instant.

Equations

• y[n]=h0*a[n] + sum h[k]*a[n-k]

Units

UI, mV

Validity

Linear time-invariant channel; no equaliser unless stated.

Numerics

Shared kit channel; cursor at the single-bit peak.

Known limitations

Linear time-invariant channel; no equaliser unless stated.

Evidence

check-models.js — CTLE and DFE suites share this channel model.

Show how TJ depends on the BER you name.

Topology

As bathtub.

Reference planes

Receiver decision point.

Equations

• Q(BER) by bisection on the Gaussian tail integral

Units

ps, UI

Validity

Gaussian tails assumed; a periodic component is fitted badly.

Numerics

Same erfc treatment as the bathtub.

Known limitations

Gaussian tails assumed; a periodic component is fitted badly.

Evidence

check-models.js — Bathtub suite, shared model.

Show the two loss terms crossing, and where the crossover moves.

Topology

One uniform line; attenuation per unit length only.

Reference planes

Per inch — a rate, not a channel.

Equations

• a = kc*sqrt(f) + kd*f
• delta=sqrt(rho/(pi*f*mu))

Units

Hz, dB/in, um

Validity

A FIT, not a geometry solve. Roughness shown as shape, not a calibrated prediction.

Numerics

Direct evaluation.

Known limitations

A FIT, not a geometry solve. Roughness shown as shape, not a calibrated prediction.

Evidence

check-numbers.py — skin depth at 1 and 10 GHz recomputed.

Show what one LPDDR6 sub-channel burst carries, why a 1 costs energy on an LVSTL bus, what DBI saves, and what choosing link protection instead gives up.

Topology

One sub-channel burst, 12 DQ x BL24 = 288 bits, drawn by content: 256 data bits in sixteen 16-bit groups, 16 metadata bits, 16 DBI flags or link-protection check bits.

Reference planes

The DRAM's data pins.

Equations

• DBI: invert a 16-bit group when it holds more than eight 1s, and send a 1 flag for it
• energy of a 1 = VDDQ^2/(Ron + RTT) x UI, with VDDQ 0.5 V and Ron = RTT = 40 ohm
• link-protection check bits counted at their average, 8 ones of 16

Units

bits, pJ, fJ

Validity

Termination energy only; the transition energy of charging lines and pins is left out.

Numerics

Exact counting.

Known limitations

A logical layout, not the standard's pin-and-beat map; the DBI grouping follows vendor descriptions of the standard, not the standard itself; the check bits' values depend on a code the panel does not implement.

Evidence

check-models.js - LPDDR6 page (DBI counting and the energy of a 1).

Say where a coupled digital aggressor lands in a converter's output — as spurs, as offset, or as raised noise — and what that does to SNR, for a SAR and a delta-sigma converter fed the same disturbance.

Topology

Two converters, one aggressor. SAR: ideal bipolar sample-and-hold, then N bit trials spread over the first half of the sample period, each comparing the held input with a DAC scaled by the reference at that trial's own instant. Delta-sigma: discrete-time, second order, one bit, reference multiplying the feedback DAC, followed by sinc-cubed decimation of length 3·OSR−2. The aggressor is a 50%-duty trapezoid with linear edges through a single RC pole, in periodic steady state.

Reference planes

Injection at the converter input or at its reference, chosen explicitly. Observation is the decimated output record for the delta-sigma and the code record for the SAR; the modulator bitstream is separately observable. The aggressor is evaluated in the time domain at the exact instants the converter uses it — the sampling instant for the input path, each bit trial for the SAR reference, each modulator clock for the delta-sigma.

Equations

• aggressor: 50%-duty trapezoid, 10-90% rise/fall, full ramp = that / 0.8, through one pole at the path bandwidth
• flat coupling: v = G·y(t); capacitive: v = G·(f_bw/f_ref)·(x - y), i.e. G/(2*pi*f_ref)·dy/dt with G stated at f_ref = 1 MHz
• fold: f_out = |f - round(f/fs)·fs|
• SAR trial j: c <- c + 2^(N-1-j) if h >= (Vref + d(t_j))·(2c/2^N - 1)
• delta-sigma, for the implemented ordering: X1 = (U-V)/(1-z^-1), X2 = (X1-V)/(1-z^-1), V = z^-1·X2 + E, giving V = z^-1·U + (1-z^-1)^2·E because (1-z^-1)^2 + z^-1(2-z^-1) = 1
• sinc-cubed: three cascaded length-OSR moving averages; |H(f)| = |sin(pi·f·OSR/fmod)/(OSR·sin(pi·f/fmod))|^3
• SNR excludes the fundamental, input harmonics 2-6 and DC, each +/-4 bins; interference counts as noise

Units

Hz, seconds, volts, dBFS, dB, LSB, ppm

Validity

Ideal comparator, DAC, sample-and-hold and clocks. One periodic trapezoidal aggressor. Oversampling is capped at 256 so a run stays interactive. Every parameter is checked against a declared domain before a run — enums, a finite positive reference, whole-number resolution 6-24 and oversampling 8-1024, an input below Nyquist and at or below full scale, finite non-negative noise, swing, phase, ppm, coupling and bandwidth, a positive rise/fall time — and a value outside it is refused with its reason. A reference driven to zero or below is refused, and so is an overloaded loop.

Numerics

SAR 65,536 samples at 16 bits. Delta-sigma output records are chosen from the oversampling ratio to hold the cost near a million modulator samples: 16,384 outputs at OSR 32 and 64, 8,192 at 128, 4,096 at 256, after a warm-up of 4,096 + 8·OSR modulator samples plus a full decimator kernel. Coherent input: an odd number of cycles in a power-of-two record, kept two lobes clear of DC and Nyquist. 4-term Blackman-Harris window, lobes summed over +/-4 bins. Deterministic noise seed. One run is synchronous and cannot be cancelled part way: measured at 14 ms for the SAR and 38-89 ms for the delta-sigma, so a dragged control coalesces to one run.

Known limitations

No clock jitter or aperture uncertainty, no supply or ground bounce as a separate path, no DAC mismatch, no continuous-time or multi-bit modulator, no anti-alias filter beyond the single path pole. DNL and INL are named as mechanisms and are NOT measured: there is no static ramp or histogram test here, and THD is not a substitute for one. Interference that folds inside an excluded lobe is excluded with it and does not reduce the reported SNR, however large it is; diagnostics.masked names any such component and measurements.maskedCount counts them. The excluded bins carry no measurable noise of their own, so the measured average density stands in for them: exact for white noise, and otherwise bounded by the replaced fraction, which is under 0.2% of bins and so under 0.01 dB. The reference-ripple mixing shown is a property of this loop and does not transfer unchanged to a continuous-time or multi-bit modulator. Nothing here is a compliance measurement.

Evidence

check-models.js, eight named suites, 47 assertions, none of which re-runs the model's own formulas. The loop's transfer function is checked by inverting its claim: the double integral of (V - z^-1·U) must BE the quantization error, bounded by the reference plus the overload threshold and consistent with the decision that produced it, which holds at 7.73 V against a 42.5 V bound with no sign violations and fails at 130 V for any other delay. Spur levels come from the trapezoid's Fourier series through a least-squares tone fit to the output record, agreeing within 0.2 dB. Ideal SAR SNR is checked against 6.02N + 1.76 at 10, 12 and 16 bits; the delta-sigma against 15.05 dB per doubling and the closed-form 1-bit second-order limit. Folds are checked against a remainder-and-mirror construction. The decimator is checked against the properties of three cascaded boxcars. Scenario prose is guarded separately by tests/check-adc-integration.js (56 values) and the page's closed forms by check-numbers.py (21). Twelve planted faults in mutate.js, each required to fail the assertion that claims it.

Show a peak appearing between two capacitor banks, and what damps it.

Topology

Two RLC branches in parallel, plus the VRM branch.

Reference planes

One port at the load.

Equations

• Zpeak ~ L/(R*C)
• fSRF=1/(2*pi*sqrt(LC))

Units

Hz, ohm

Validity

Lumped; no plane modes.

Numerics

Direct complex evaluation; explicit no-peak state when none exists.

Known limitations

Lumped; no plane modes.

Evidence

check-models.js — PDN (anti-resonance exists and is damped by R; no phantom peak when flat).

Show the measured region and the extrapolated region as different things.

Topology

Dual-Dirac: two impulses separated by DJ, convolved with a Gaussian.

Reference planes

Receiver decision point.

Equations

• BER(t)=0.5[Q((t-DJ/2)/s)+Q((UI-DJ/2-t)/s)]
• TJ=DJpp+2*Q(BER)*RJrms

Units

UI, s

Validity

Dual-Dirac is a FIT, not a measurement of the deterministic width.

Numerics

erfc below x=3, asymptotic series above; explicit empty result when no interval meets the target.

Known limitations

Dual-Dirac is a FIT, not a measurement of the deterministic width.

Evidence

check-models.js — Bathtub (closed eye returns no interval; crossings match the analytic Q inverse).

Q factor and total jitter implied by a target BER under the dual-Dirac model.

Topology

Gaussian random jitter plus dual-Dirac deterministic jitter, transition density 0.5 or 1.

Reference planes

The receiver's sampling point.

Equations

• BER = rho*Q(Q_BER)
• TJ = DJ(dd) + 2*Q_BER*RJ

Units

s, dimensionless

Validity

RJ Gaussian into the extrapolated tail; DJ given as its dual-Dirac value.

Numerics

Chebyshev erfc below x = 3, four-term asymptotic series above; the branches differ by about 0.9% at x = 3. Inverse by bisection.

Known limitations

Dual-Dirac DJ is a fitted quantity, smaller than peak-to-peak DJ; no amplitude noise.

Evidence

check-models.js — Calculator: BER, Q and total jitter (tail identities, normal table, the published 14.069 multiplier).

Symbol rate, unit interval, Nyquist frequency, edge bandwidth and bits in flight from a data rate.

Topology

NRZ or PAM4 random data; a single-pole edge; a uniform trace.

Reference planes

Transmitter output.

Equations

• UI = bits_per_symbol/data_rate
• f_Nyquist = 1/(2*UI)
• f_3dB = 0.35/tr

Units

b/s, Bd, s, Hz

Validity

Random equiprobable symbols; 0.35/tr exact for a single pole only.

Numerics

Closed form; sinc^2 spectrum sampled for the plot.

Known limitations

A Gaussian edge gives 0.34 rather than 0.35.

Evidence

check-models.js — Calculator: bit rate, UI and Nyquist (UI x baud = 1, PAM4 vs NRZ, single-pole ln(9)/2pi, spectral null).

Delay, round trip and critical length of a trace at a given rise time.

Topology

One driver, one receiver, a uniform line.

Reference planes

Driver and receiver pins.

Equations

• tpd = 84.72*sqrt(Dk_eff) ps/in
• electrically long when 2*Td > tr/3

Units

s, in

Validity

Uniform lossless line; the /3 is a convention.

Numerics

Closed form.

Known limitations

The /3 criterion is a convention shared with the topic page, not physics.

Evidence

check-models.js — Calculator: electrical length (speed of light at Dk 1, round trip exactly tr/3 at the critical length, agreement with the topic page).

Characteristic impedance, effective permittivity and delay of microstrip and centred stripline.

Topology

Microstrip on a homogeneous dielectric; zero-thickness stripline centred between planes.

Reference planes

The line cross-section.

Equations

• microstrip: Hammerstad-Jensen (1980) with thickness correction
• stripline: Z0 = (eta0/(4*sqrt(er)))*K(k)/K(k'), k = sech(pi*w/2b)

Units

ohm, mil

Validity

Quasi-static; no dispersion, no solder mask, rectangular copper.

Numerics

Closed form; elliptic integrals by the arithmetic-geometric mean; width solved by bisection.

Known limitations

Stripline is zero-thickness; real copper reads a few ohms lower.

Evidence

check-models.js — Calculator: microstrip and stripline impedance (Wheeler within 1%, air limit, parallel-plate limit, IPC-2141, lemniscate constant).

Insertion loss of a PCB channel against a budget.

Topology

A uniform TEM line in one dielectric; current on one face of the strip; lossless return path.

Reference planes

Channel ends.

Equations

• alpha_d = pi*f*sqrt(Dk)*Df/c
• alpha_c = Rs*K/(2*w*Z0)

Units

dB, dB/in, Hz

Validity

Constant Dk and Df; first-order conductor loss, roughly +/-30% of a field solve.

Numerics

Closed form.

Known limitations

Conductor loss ignores current sharing between faces and return-plane loss.

Evidence

check-models.js — Calculator: loss budget (zero Df, linear dielectric loss, sqrt(f) conductor loss, Bogatin rule within 5%).

Loop inductance of the via pair under a decoupling capacitor, and the mounted self-resonance.

Topology

Two parallel round vias of equal length down to a plane pair.

Reference planes

Capacitor pads to the plane pair.

Equations

• L = (mu0*h/pi)*acosh(s/d)
• f_SRF = 1/(2*pi*sqrt((ESL + L)*C))

Units

H, mil, Hz

Validity

The via pair only.

Numerics

Closed form, via K.viaLoopInductance.

Known limitations

Pad, trace and plane-spreading inductance are not included; this is a lower bound.

Evidence

check-models.js — Calculator: mounting inductance (thin-wire limit at s = 50d, linear in length, touching vias).

Cavity modes of a rectangular plane pair.

Topology

A bare rectangular plane pair with open (magnetic-wall) edges.

Reference planes

The plane pair.

Equations

• f(m,n) = (c/(2*sqrt(Dk)))*sqrt((m/a)^2 + (n/b)^2)

Units

Hz, mm

Validity

Thin cavity, no fringing, no components.

Numerics

Closed form; modes enumerated to 30 per axis.

Known limitations

Fringing lowers the modes slightly; capacitors and vias move and damp them.

Evidence

check-models.js — Calculator: plane cavity resonance (c/2a in air, square-plate degeneracy, harmonic ratios).

Convert between return loss, reflection coefficient, VSWR and a resistive load.

Topology

A resistive load on a lossless line of reference impedance Z0.

Reference planes

The load terminals.

Equations

• Gamma = (RL - Z0)/(RL + Z0)
• RL = -20*log10|Gamma|
• VSWR = (1+|Gamma|)/(1-|Gamma|)

Units

dB, ohm

Validity

Resistive loads; for a complex load the magnitude relations hold but the load is not unique.

Numerics

Closed form.

Known limitations

Return loss, |Gamma| and VSWR do not fix the sign, so two loads are reported.

Evidence

check-models.js — Calculator: return loss, reflection coefficient, VSWR (matched, open and short limits; round trips; power conservation).

Resonant frequency, Q, bandwidth and impedance of an RLC circuit or a real capacitor.

Topology

Ideal series or parallel R, L and C; capacitor mode is series R = ESR, L = ESL.

Reference planes

The two terminals of the circuit.

Equations

• f0 = 1/(2*pi*sqrt(L*C))
• Q = sqrt(L/C)/R (series), R/sqrt(L/C) (parallel)
• f1,2 = f0*(sqrt(1+1/4Q^2) -/+ 1/2Q)

Units

Hz, ohm, H, F

Validity

Frequency-independent R, L and C.

Numerics

Closed form; |Z| sampled on a log grid for the plot.

Known limitations

Constant ESR in capacitor mode; no DC-bias derating.

Evidence

check-models.js — Calculator: LC/RLC resonance (purely resistive at f0, half-power edges, f1*f2 = f0^2, asymptotes).

Copper skin depth, surface resistance, skin-effect onset and the roughness multiplier.

Topology

A copper conductor at 20 C, thick compared with the skin depth above onset.

Reference planes

The conductor surface.

Equations

• delta = sqrt(rho/(pi*f*mu0))
• Rs = rho/delta
• K = 1 + (2/pi)*atan(1.4*(Rq/delta)^2)

Units

m, ohm/sq, Hz

Validity

Copper, rho = 1.68e-8 ohm*m; roughness model valid to a few tens of GHz.

Numerics

Closed form.

Known limitations

Hammerstad-Bekkadal roughness is a fit on RMS roughness and saturates at 2.

Evidence

check-models.js — Calculator: skin depth and roughness (2.06 um at 1 GHz, 1/sqrt(f), roughness limits).

Quarter-wave notch of a via stub against the channel's Nyquist frequency.

Topology

An ideal open stub of the line's impedance shunted across a matched line.

Reference planes

The via's through-path.

Equations

• f_notch = c/(4*l*sqrt(Dk_eff))
• S21 = 2/(2 + j*tan(pi*f/(2*f_notch)))

Units

Hz, mil, dB

Validity

Lossless stub of the line's impedance; the notch frequency is the robust output.

Numerics

Closed form.

Known limitations

A real stub has loss and a different impedance, so its notch is finite and its shoulder shifts.

Evidence

check-models.js — Calculator: via stub resonance (quarter wavelength at the notch, half-wave transparency, 4/5 at half the notch).

Separate the three functions a clock-recovery loop defines: input jitter onto the recovered clock, the residual phase error at the decision, and the input jitter the receiver can withstand.

Topology

Second-order type-2 loop. No phase-detector model, no VCO model, no data pattern.

Reference planes

Phase at the receiver's decision instant, relative to the incoming data.

Equations

• H(s) = (2*zeta*wn*s + wn^2) / (s^2 + 2*zeta*wn*s + wn^2)
• residual = COMPLEX 1 - H(f), never 1 - |H(f)|
• tolerance = margin / |1 - H(f)|, capped by a declared tracking ceiling
• f3dB: u^2 - (2 + 4*zeta^2)*u - 1 = 0 with u = (w/wn)^2, so f3dB = fn*sqrt(root)
• steady-state sinusoid: recovered phase = H(f) times input phase; residual = input - recovered

Units

Hz, seconds, UI peak-to-peak, dimensionless transfer

Validity

A teaching loop with declared parameters: natural frequency, damping and sampling margin. The sinusoidal experiment is the steady-state small-signal response after settling. The low-frequency tracking ceiling is DECLARED, not derived — a real one comes from the phase detector's range and the VCO's tuning. fn is the NATURAL frequency and is reported separately from the closed-loop -3 dB bandwidth, which is 1.58x to 3.37x higher depending on damping.

Numerics

Direct complex evaluation on 340 log-spaced points from 1 kHz to 1 GHz; 181 analytic sinusoidal samples over three periods at the selected frequency.

Known limitations

Not a lock or acquisition transient, cycle-slip model, BER simulation, or compliance jitter-tolerance mask. A mask carries a BER target, a defined pattern, the phase detector's own characteristic and usually a measured low-frequency corner. This model has none of those, and the dashed part of the tolerance curve is an assumption drawn as one. No noise model: the panel makes no claim about how much of the loop's own reference noise reaches the recovered clock, because that needs a spectrum and an injection point and neither is here. The tracking ceiling is a DECLARED assumption, not a derived result, and where it binds the tolerance no longer scales with the sampling margin.

Evidence

check-models.js — CDR loop: the analytic asymptotes (|1-H| -> 1 far above the loop so tolerance equals the bare margin; |1-H| -> (f/fn)^2 far below), H(0) = 1 exactly, the complex complement distinguished from 1 - |H|, and type-2 peaking present at every damping. N3-1: the -3 dB bandwidth is checked against a closed form solved by hand from |H|^2 = 1/2 and, independently, against where the swept |H| crosses 1/sqrt(2) with log-interpolation between grid samples. The residual peak is asserted to EXCEED unity whenever the loop is underdamped, and the worst tolerance to fall below the sampling margin with it. Three assertions record that a fixed axis limit of 3, and a tolerance floor of half the margin, would clip the extrema the damping control exists to produce.

Show capacitive pickup following the aggressor's voltage slew and the victim's impedance, and inductive pickup following its current slew, from one aggressor, in time and in frequency.

Topology

One trapezoidal aggressor (resistive or capacitive load); mutual capacitance into a victim node R_v ∥ C_v; mutual inductance into a victim loop with one pole.

Reference planes

The victim node (capacitive) and the victim loop (inductive).

Equations

• capacitive: H_C(s) = s*R_v*Cm / (1 + s*R_v*(Cm + Cv))
• inductive, resistive load: EMF = M*dI/dt = (M/R_L)*dV/dt, through one pole at f_L
• inductive, capacitive load: EMF = M*C_L*d2V/dt2, through one pole at f_L
• crossover (resistive load): Z* = M/(Cm*R_L)

Units

V, A, s, ohm, F, H, dBV

Validity

Lumped: the coupled structure is short against the edge. Cm = 0.5 pF, M = 1 nH, Cv = 5 pF, f_L = 1 GHz and a 10 MHz, 50% duty aggressor are held fixed and stated on the panel.

Numerics

Exact periodic steady state, segment by segment (piecewise-constant slope, or impulses for a capacitive load); spectrum from the transfer functions.

Known limitations

No distributed (transmission-line) coupling, no path resonance, no shared-impedance path; one pole per path.

Evidence

check-models.js — Coupling (20 and 40 dB/decade slopes, the Cm/(Cm+Cv) plateau, slow-edge closed forms, independence of each path from the other driver, the Z* crossover, an exact Fourier integral of the time-domain solution against the transfer functions, zero mean, 6.02 and 12.04 dB edge-rate bounds).

Show how C-PHY carries data and clock on three wires: a 16-bit word as seven symbols, each a move to one of the five other wire states, the three wire voltages and the three differential receivers, and why the receivers' eye has more than one crossing and is sensitive to one late wire.

Topology

One trio, wires A, B and C, each driven at high, mid or low with a raised-cosine edge, optionally through the shared channel model; wire C optionally delayed. Three receivers: A - B, B - C and C - A.

Reference planes

The three wires at the receiver and the three differential receiver outputs.

Equations

• levels in steps: high +1, mid 0, low -1; receivers read +-1 or +-2
• (A - B) + (B - C) + (C - A) = 0
• word -> seven base-5 digits; digit d selects the d-th of the five other states (a valid mapping, not the specification's table)
• rate per trio = symbol rate x 16 / 7

Units

Gsps, ps, dB, steps of the mid-to-high level

Validity

Linear wires with matched loss and no coupling between them; ideal level drivers.

Numerics

32 samples a symbol; the channel is K.channelImpulse convolved with each wire, its bulk delay removed; the eye is 36 random words folded over the symbol, its width the share of phases where every receiver is on the right side by at least 0.2 of the weak level.

Known limitations

The mapper is a valid one chosen for the page, not the specification's table, which is members-only, as are the voltages. No receiver equalisation, no coupling within the trio, no termination network, no 18-wirestate mode and no D-PHY mode. Mechanism and proportion, not a sign-off.

Evidence

check-models.js suite C-PHY trio: one wire is at mid in every state, the receivers sum to zero and never read zero, and the six states give six sign patterns; all 65,536 words round-trip through seven symbols of 0 to 4, and from every start no symbol leaves the state unchanged and every symbol flips a receiver; the receivers sum to zero at every sample through edges, skew and loss; matched wires with no loss open fully to the weak level; skew, slower edges and loss never widen the eye; seven symbols are the fewest that hold 16 bits.

Show what a 2D quasi-TEM field solver does with a trace cross-section, and the two checks every solver result needs: does the answer stop moving as the mesh is refined, and does it move when the walls of the solve are moved.

Topology

One trace, or a pair driven in odd or even mode, as microstrip over one plane or as stripline centred between two, in a laminate of one Dk. Width, height, copper thickness and gap in mils. The solve is closed by grounded walls a set number of trace heights from the copper.

Reference planes

The potential everywhere in the cross-section, its equipotentials and flux lines, the capacitance per length with the laminate and in air, and from them Z0 (or Zdiff, Zcomm), eeff, and L and C per inch.

Equations

• div(eps grad phi) = 0, phi = 1 V on the trace, 0 on the planes and walls; odd mode: phi = 0 on the plane of symmetry, even mode: d phi/dn = 0
• bilinear (Q1) finite elements on a graded tensor mesh; C = 2 W / V^2 with W = (1/2) phi^T K phi
• Z0 = 1 / (c sqrt(C Cair)), eeff = C / Cair, L = 1 / (c^2 Cair)
• Zdiff = 2 Zodd, Zcomm = Zeven / 2
• limit by Aitken's delta-squared on the meshes of 4, 8 and 16 cells

Units

mil, ohm, nH and pF per inch

Validity

Quasi-TEM: the cross-section is small against a wavelength, the conductors are perfect and the dielectric lossless, so Z0 is the high-frequency, lossless value. Microstrip is quasi-TEM and its eeff rises with frequency, which this does not show.

Numerics

Half the cross-section, mirrored. The mesh is finest at the copper edges (d/n, d the smallest of w, h and the gap), 1.5 d near the trace, and grows by 1 + 2/n per cell beyond; banded Cholesky numbered along the shorter side. Seven mesh levels, 2 to 16 cells; the wall sweep uses 8.

Known limitations

No loss, no frequency dependence, no solder mask, no etch trapezoid and no roughness. One dielectric for a stripline; microstrip is laminate below the trace bottom and air above. Grounded walls stand in for open space, which is what the boundary plot is there to show. Mechanism and proportion, not a sign-off number.

Evidence

check-models.js suite Cross-section: the extrapolated Z0 of a zero-thickness stripline matches Cohn's exact conformal-map answer within 0.1%, every mesh is below it and the extrapolation is nearer than the finest mesh; a stripline's eeff is its Dk exactly and Z0 scales as 1/sqrt(er); doubling every dimension leaves Z0 unchanged; Z0 rises at every mesh refinement; a microstrip agrees with Hammerstad-Jensen within 0.5%; a 30:1 strip sits just below the parallel-plate Z0; Z0 never falls as the walls move out; odd mode is below even mode in Z0 and eeff, both tend to the single line 20 h apart, and a stripline pair has equal modal eeff.

Show why near-end saturates and far-end accumulates.

Topology

Single coupled pair, uniform section, weak coupling.

Reference planes

Both ends of the victim.

Equations

• Kb=(Lm/L0+Cm/C0)/4
• Kfe proportional to (Lm/L0-Cm/C0)

Units

ps, mV

Validity

Weak coupling, ratios <= 0.30. One aggressor, not a bus.

Numerics

Closed form superposition over the coupled length.

Known limitations

Weak coupling, ratios <= 0.30. One aggressor, not a bus.

Evidence

check-models.js — Crosstalk (FEXT cancels when the ratios are equal; NEXT saturates past tr/2tpd).

Compare the bandwidth that published UCIe and BoW layouts put through each millimetre of die edge, and through each square millimetre of bumps once the bump pitch is taken out.

Topology

No channel: arithmetic on four published layouts, the UCIe-S and UCIe-A modules (C-76) and BoW's example link on laminate and on an interposer (C-87).

Reference planes

Die edge and bump field, both directions counted.

Equations

• edge density = data wires * wire rate / 8 / edge width
• UCIe-S at 48 and 64 GT/s: the consortium table (C-68)
• bump density = data wires / 8 / (edge * depth), per Gb/s of wire rate
• at a common pitch: bump density * (own pitch / common pitch)^2
• UCIe bump density: the range over its published readings (C-76, C-100)

Units

Gb/s per wire, GB/s/mm, GB/s/mm2 per Gb/s, um

Validity

Exact arithmetic on the published dimensions. Each layout is one example, not the only layout a standard allows; BoW does not specify bump patterns, and its two examples are one layout at two pitches.

Numerics

Direct evaluation at the nine wire rates the standards define.

Known limitations

The UCIe sources disagree on bump density: the module rectangle is labelled 55 um on one slide while the consortium's table states 45 um, and the table's areal row is about 1.3 times denser than the rectangles. The panel shows the range rather than choosing. AIB gives no comparable layout and is not drawn. Bump density counts the whole rectangle a layout occupies. The pitch scaling assumes the same bump arrangement, and the circuits still fitting, at the new pitch.

Evidence

check-models.js suite Chiplet layouts: the BoW example's own 2.0 Tb/s each way, the UCIe module widths reproducing the consortium's shoreline table, bandwidth proportional to wire rate at fixed geometry, the inverse-square pitch law, the UCIe range spanning every published reading, undefined rates reported as undefined, and malformed inputs refused. check-numbers.py recomputes every figure the prose states.

Show how a DDR5 data net with one or two DIMMs behaves in time: where each reflection comes from and which later bit it lands on, what the terminations trade, what the DRAM's 4-tap DFE can and cannot cancel, and what training sees.

Topology

Controller die (1.0 pF) and package, a 40 ohm mainboard trace to slot 1, optionally a slot-to-slot trace to slot 2; at each populated slot a 60 ohm, 25 ps connector, 20 mm of 40 ohm DIMM trace, a 45 ohm, 30 ps package and a 0.8 pF DRAM die; an empty slot is its connector, open. Single-rank DIMMs.

Reference planes

Controller die and DRAM die nodes; the eye is at the receiving die, after the DFE summer on writes.

Equations

• Method of characteristics: V = (sum 2 a_i/Z_i + Vs/Rs + J_C)/(sum 1/Z_i + 1/Rs + 1/RTT + 2C/dt); each line carries V - a_i away
• Capacitors by the trapezoidal companion: i = (2C/dt) v - J, J' = (2C/dt) v + i
• POD swing = VDDQ RTT_eff/(Ron + RTT_eff), RTT_eff every termination in parallel
• pulse p(t) = s(t) - s(t - UI); worst-case eye h0 - sum|h_k - c_k|, c_k the DFE taps on k = 1..4
• DFE taps clipped to the data sheet ranges (t1 -200..+50, t2 +/-75, t3 +/-60, t4 +/-45 mV, 5 mV steps, |t2|+|t3|+|t4| < 60 mV)

Units

ps, V, mV, ohm, pF, mm

Validity

Lossless TEM lines at 6.7 ps/mm with whole-picosecond delays; lumped die capacitance; linear drivers and terminations; single-rank DIMMs; no crosstalk, SSN or supply noise; the driver edge is a raised cosine of 30% of a UI, held between 30 and 70 ps.

Numerics

1 ps time step over the whole tree; pulse sampled at 32 points a UI; PRBS-11 eye with 64 bits of history; training phase chosen within one UI of the pulse peak by the worst-case eye; shmoo with seeded 5 mV rms noise and 2 ps rms jitter, VrefDQ in 0.5% of VDDQ steps; termination sweep of 8 x 8 runs.

Known limitations

No loss, so long mainboard routes are optimistic; no crosstalk or SSN; the controller's read equalisation is not modelled; the stressed-eye diamond is the receiver's test condition, not a channel mask; the shmoo's noise is a model choice. No ESD clamps or loss, so an open stub rings past both rails further than silicon would allow.

Evidence

check-models.js — DDR5 page (the solver matches an independent frequency-domain nodal solution of the same net; a matched line, an open end and a three-way junction give their closed-form levels; the settled level equals the POD divider; the peak-distortion bound equals a brute-force search of every pattern; DFE taps stay inside their ranges and the sum limit; a DFE cannot touch the fifth post-cursor; an unterminated second DIMM closes the eye that a terminated one leaves open; the far slot leaves a larger eye than the near one with one DIMM fitted; the largest post-cursor is the near branch's round trip when the far DIMM is terminated, does not move with the far slot and shrinks when the target is terminated, and becomes the far branch's round trip when the far DIMM is not; the trained point lies inside the passing region; the PRBS eye equals the whole bit stream driven through the solver; every PRBS eye is at least its worst-case bound).

Show why a fly-by clock reaches each DRAM at a different time, how the DRAMs' input capacitance slows and lowers the line, and what write leveling has to add to each lane's strobe.

Topology

An RCD driver (25 ohm) into 12 mm of 50 ohm line to DRAM 0, then one pitch of the same line between each of five DRAMs, each a lumped input capacitance, ending in the last DRAM's CA termination.

Reference planes

Each DRAM's input node.

Equations

• Method of characteristics, as the DDR5 bus model
• loaded line: t_pd' = t_pd sqrt(1 + C_load/C_line), Z' = Z0/sqrt(1 + C_load/C_line), C_line = t_pd pitch/Z0
• arrival = the 50% crossing of the settled level at each DRAM

Units

ps, mm, pF, ohm

Validity

Single-ended, lossless line at 6.7 ps/mm; one subchannel's five DRAMs; the strobes are taken to arrive together, as from equal-length point-to-point routes.

Numerics

1 ps time step; 60 ps 10-90% edge; arrivals by linear interpolation of the 50% crossing.

Known limitations

The clock is drawn single-ended and as one edge; the RCD's own delay and the controller-to-RCD flight are left out, so times are from the RCD's output; the DRAMs nearer the RCD carry no termination.

Evidence

check-models.js — DDR5 page (with no load every gap costs the unloaded flight; with load the delay per DRAM approaches the loaded-line formula; more load never arrives sooner).

Show where a differential pair's common mode comes from: how a length mismatch, a glass-weave velocity difference, a drive imbalance or one slower edge turns part of the differential signal into common mode, what that does to SDD21 and SCD21, and how little of it the differential eye shows.

Topology

Two uncoupled legs, P driven with PRBS7 and N with its complement, each a gain, a delay and a single-pole edge. The skew delays P by half and advances N by half. Glass-weave skew is the routed length at two velocities, Dk 4 against Dk 4 + dDk.

Reference planes

The two legs at the receiver; the differential and common-mode voltages formed from them.

Equations

• H_k(f) = g_k exp(-j 2 pi f d_k) / (1 + j 2 pi f tau_k), tau = t_r / ln 9
• S_DD21 = (H_P + H_N)/2, S_CD21 = (H_P - H_N)/2
• V_diff = V_P - V_N, V_cm = (V_P + V_N)/2
• weave skew = L (sqrt(Dk + dDk) - sqrt(Dk)) / c
• emission vs one wire: peak over f of f |S_CD21| |sinc(f T)|, against the same for one wire driven alone

Units

ps, GHz, V, in, dB

Validity

Uncoupled, lossless legs with single-pole edges. Common mode is what the asymmetry makes, before any receiver rejects it.

Numerics

One full PRBS7 period at 32 samples per bit, every edge summed in closed form including earlier periods until the slowest edge has settled. Eye folded at the phase that leaves it whole; its width is the share of the UI open by at least 10% of the swing. 240 frequency points to twice the bit rate.

Known limitations

No coupling between the legs, so no odd- and even-mode velocity difference and no Zdiff; the field solver page does that. No channel loss, no reflections, no receiver CMRR. The emission figure is a relative proxy for a short cable's radiation, not an emissions limit.

Evidence

check-models.js suite Differential pair: identical legs give no common mode and no SCD21 at all; for skew alone |SDD21|^2 + |SCD21|^2 equals one leg's |H|^2 and SDD21's first null falls at 1/(2 skew); the common-mode pulse of one edge has area -A skew / 2 whatever the edge shape; swapping the legs flips the common mode and leaves |SCD21| alone; a drive imbalance alone gives SCD21/SDD21 = a/2 at every frequency; doubling a small skew adds 6 dB of emission; the eye never widens as skew grows.

Show why a DisplayPort or HDMI link's rate is decided by loss at each rate's own Nyquist frequency: a path from source die to sink die through boards, connectors and a cable, with an optional retimer, checked against each rate's budget from the top rate down, the way link training steps down.

Topology

Source package, source board trace, mated connector, cable, mated connector, sink board trace, sink package. A retimer beside either connector splits the path into two segments, each with a package of the retimer's.

Reference planes

Die to die, per segment.

Equations

• board: dielectric pi f sqrt(Dk) Df / c plus conductor Rs K / (2 w Z0), the laminate's published Dk and Df (NS.calc.loss)
• cable pair: Z = (120/sqrt(er)) arccosh(D/d); R' = (2 Rs / pi d) (D/d) / sqrt((D/d)^2 - 1); loss = k R'/2Z + pi f sqrt(er) tan(d) / c, k fitted to C-118
• package, connector: illustrative allowance at 10 GHz x (0.35 sqrt(f/10 GHz) + 0.65 f/10 GHz)
• a rate trains if every segment's loss at its Nyquist is within its budget; the link takes the highest that does
• payload = lanes x rate x coding (8/10 or 128/132)

Units

dB, GHz, Gb/s, in, m, AWG

Validity

Insertion loss only: smooth, matched segments whose decibels add. Budgets are die-to-die figures at Nyquist from public vendor material (DisplayPort UHBR and HBR3; HDMI FRL 12G, from a worst-case cable test channel, which makes HDMI cautious) or assumed (the other rates).

Numerics

Closed form at each rate's Nyquist; the loss chart samples each segment at 111 frequencies to 11 GHz.

Known limitations

A loss budget, not an eye: no reflections, return loss, crosstalk, jitter or equalisation, so a path that fits can still fail and one that misses by a little can still train. Package and connector allowances, the cable's insulation and the budgets of RBR, HBR, HBR2 and every HDMI rate but FRL 12G are illustrative or assumed; HDMI's 20 dB is a cable test channel counted die to die, so its verdicts are cautious; the cable is a two-wire pair scaled by one factor fitted to one public twinax figure. The drive-level steps of clock recovery and the 128b/132b training sequence are not modelled. The HDMI order of retrying lower FRL rates before TMDS is not public; the ladder is the shape of the decision. Not the VESA or HDMI compliance test.

Evidence

check-models.js suite Display link: the coding efficiencies are the bit ratios and HBR3 on four lanes reproduces VESA's published 25.92 Gb/s; the cable loss goes as the square root of frequency with no insulation loss, its proximity factor tends to one for widely spaced wires and exceeds one at 100 ohms, thinner wire always loses more, and the fitted factor is at least one; every segment's loss is zero at DC and rises with frequency; the trained rate fits its budget and every higher rate up to the cap does not; a longer cable, a longer trace or a thinner gauge never trains a higher rate, a retimer never a lower one, and lowering the cap never raises the rate. HDMI: FRL is 16b/18b on three lanes at 3 and 6 Gb/s or four at 6 to 12 with no clock lane, TMDS three data lanes beside a clock; FRL 12G carries 48 x 16/18; the ladder tries every FRL rate before TMDS, and with equal budgets loss alone never lands an FRL sink in TMDS.

Separate what each equaliser block can and cannot reach.

Topology

Shared channel impulse, then CTLE and/or DFE.

Reference planes

Receiver input and slicer input.

Equations

• H(s)=(1+s/wz)/((1+s/wp1)(1+s/wp2))
• DFE subtracts h[k]*a[n-k] for k>0

Units

UI, V

Validity

Ideal or decision-directed DFE as selected; no adaptation dynamics.

Numerics

Half-open tap window; CTLE normalised to unity peak gain.

Known limitations

Ideal or decision-directed DFE as selected; no adaptation dynamics.

Evidence

check-models.js — CTLE (causality, normalisation) and DFE (exact cancellation, window width).

Show what doubling the Ethernet lane rate costs on the same board trace: loss per inch at the 112G and 224G Nyquist frequencies, the reach a budget buys at each, and the single-bit pulse each rate gets.

Topology

One stripline leg of a 90 ohm differential pair, 6 mil wide, 45 ohm odd mode (C-119's geometry), in a published laminate; board trace only, ball to ball, no packages, vias or connectors.

Reference planes

The trace alone; the 112G and 224G Nyquist frequencies, 26.5625 and 53.125 GHz (C-106, C-115).

Equations

• loss per inch = dielectric + conductor, C.loss: alpha_d = pi f sqrt(Dk) Df / c, alpha_c = Rs K / (2 Z0 w), Rs = rho / skin depth
• K = 1 + (2/pi) atan(1.4 (Rq / skin depth)^2), Hammerstad and Bekkadal
• Dk, Df at each frequency from the manufacturer's published table (js/models/laminates.js), interpolated within one measurement series
• reach = budget / loss per inch at each Nyquist
• pulse: K.channelImpulse(loss at that rate's Nyquist) then K.singleBit

Units

GHz, dB/in, dB, in, ps, fraction of the swing

Validity

First-order loss of a smooth-walled TEM line with the conductor current on one face of the strip, which equals the wide-stripline limit of strip plus planes. Laminate values are typical published values, not guaranteed.

Numerics

Loss evaluated at 1 GHz steps to 60 GHz. Pulses by FFT of a minimum-phase channel, 32 samples per unit interval, 4096 points.

Known limitations

No vias, packages, connectors, crosstalk or reflections. Narrow-strip fringing and differential coupling change the conductor loss; a measured trace (C-119, laminate not named) loses 1.25-1.40 dB/in at 53.125 GHz. FR-4 data stop at 10 GHz and are held flat above it. The pulse shape is the site's shared channel model with its fixed split of copper and dielectric loss; only the loss at each Nyquist comes from the laminate. No equalisation.

Evidence

check-models.js suite Ethernet lane: a pure-dielectric line doubles its loss per inch from 112G to 224G Nyquist and a smooth pure-conductor line rises by sqrt 2, any constant-Df mix lies between, dielectric loss per wavelength equals pi times Df, reach scales inversely with loss, the 224G pulse is lower than the 112G pulse on any trace, more loss never raises a pulse, and malformed inputs are refused. check-numbers.py recomputes every figure the prose states.

Build an eye from bits and state what the run supports.

Topology

Shared channel impulse plus Gaussian jitter.

Reference planes

Receiver input.

Equations

• superposition of 858 symbols; rule of three for the evidence floor

Units

ps, mV

Validity

Fixed sampling phase; no adaptation. 858 symbols evidences 3.5e-3, not a compliance BER.

Numerics

Seeded LFSR and seeded Gaussians — reproducible.

Known limitations

Fixed sampling phase; no adaptation. 858 symbols evidences 3.5e-3, not a compliance BER.

Evidence

check-models.js — Evidence suite (13 assertions) guards the BER floor claim.

Show why PCIe 6.0 can use a light FEC: three interleaved codes that each fix one bad byte correct any short burst in place, and the CRC and a replay take whatever is left, so the replay rate, not the raw error rate, is what the link pays for; and show how much worse bursts make it.

Topology

One 256-byte flit in one lane's byte order; byte i belongs to FEC code i mod 3 (86, 85 and 85 bytes). A flit with two or more bad bytes in any code is replayed.

Reference planes

The receiver's FEC decoder and CRC check, per flit.

Equations

• byte error rate b = 1 - (1 - FBER)^8
• errors alone: P(replay) = 1 - prod over codes of [(1 - b)^n + n b (1 - b)^(n - 1)]
• bursts: P(replay) = sum over k of C(256, k) b^k (1 - b)^(256 - k) P(fail | k bursts)
• burst length: 1 + geometric, each further byte bad with probability q
• flit time = 256 x 8 bits / (64 Gb/s x lanes)

Units

probability per flit, ns, lanes

Validity

Errors that start independently at the first-bit error rate, each extending into following bytes with a fixed probability. A proportion model of the mechanism.

Numerics

P(fail | k bursts) for k = 1 to 12 from 4000 seeded draws each, once per burst setting; a flit with more than 12 bursts is counted as failed. The closed form is used when errors arrive alone.

Known limitations

No lane striping and no bursts crossing a flit boundary; no precoding, which shortens real bursts; no miscorrection, and every flit the FEC cannot fix is assumed caught by the CRC; no model of the replay round trip, so bandwidth and latency per replay are not computed. Not the specification's reliability analysis.

Evidence

check-models.js suite Flit FEC: every burst of up to 3 bytes is corrected at every start and none of 4 to 8 bytes is; two bad bytes fail in exactly the share of pairs that share a code; at low rate the closed form is the two-error term; the burst model with no bursts meets the closed form within its own draw error; one burst fails with probability (253/256) q^3; nothing replays at zero error rate; replays never fall as the rate or the burst length grows and never exceed the flits with an error; flits last 2 ns on x16 and 32 ns on x1.

Compare four impairments on one consistent channel, as counterfactuals rather than a decomposition.

Topology

Two-term loss law, one through-section discontinuity, source and load mismatch, up to four FEXT aggressors.

Reference planes

Transmitter output to receiver input. No package.

Equations

• S21_disc=2/(2cos+j(r+1/r)sin)
• S11_in=S11_disc*e^-j2wTd1 + S21_disc^2*GL*H^2*e^-j2wTd
• echo = Gs.GL * H^2 * direct, delayed by 2*Td (first term of a geometric series in Gs.GL)

Units

s, V, ohm, dB

Validity

FIRST ORDER in the reflection coefficients: one source-load round trip is kept and the (Gs.GL)^2 terms and beyond are dropped. The relative size of what is dropped is |Gs.GL|, measured at 0.06% to 0.71% of the retained echo across the released presets and 6.3% at the controls' extremes — so it is accurate here, but it is an expansion and not a cascade. Single-ended; fixed CTLE+DFE, not adapting. For a network with every internal re-reflection included exactly, see labChannel, which cascades ABCD matrices instead.

Numerics

4096-point FFT, 32 samples/UI, 420 symbols.

Known limitations

An expansion truncated at first order, not an exact network. It also uses the two-term magnitude loss law with a minimum phase, not the causal material model that labChannel now uses, so its phase is reconstructed rather than derived.

Evidence

check-models.js — Networks and Impairment chain: the through-section loses at most 0.0481 dB and never notches, the echo is Gs.GL rather than GL^2, and the truncated series is bounded by |Gs.GL| of the retained term over the whole released range.

Show how antipads round the ground and signal vias of a BGA turn a power plane into Swiss cheese: the copper necks between them crowd the current, the DC drop climbs past a budget as they close, the power vias share the load unevenly, and when neighbouring holes touch the core is cut off.

Topology

One power plane, 20 x 11.8 mm, fed along one edge by the regulator, under a 10 x 10 corner of a BGA at 1 mm pitch: a 6 x 6 core of alternating power and ground vias inside two rings of signal and ground. Ground and signal vias pass through round antipads; each power via joins the plane at a 0.5 mm pad and runs through a plated barrel and a solder ball to the package, one common node drawing the load current.

Reference planes

The voltage and current in every cell of the plane, the current in each power via, the drop from the feed edge to the worst power via pad, and the mean current density across each neck between neighbouring antipads.

Equations

• every cell: sum over its faces of g (V_cell - V_neighbour) = 0
• a face: g = (t / rho) * copper length on the face / cell size, the copper length exact against every antipad circle
• feed edge: g = 2 (t / rho) * copper on the edge / cell size, at the regulator's potential
• a power via: g = 1 / (R_barrel + R_ball) from its pad to the package; R_barrel = rho L / (pi (D - t_plating) t_plating), R_ball = rho_SAC h / area
• the package draws I; every result scales with I
• neck density J = I_neck / ((pitch - d) t)

Units

mm, A, mV, A/mm^2

Validity

DC: no inductance, no frequency dependence. Copper at room temperature, resistance independent of current.

Numerics

Square cells of 0.2 mm, 100 x 59; a cut-cell finite-volume scheme in which each face conductance is the copper actually on it. Copper not connected to the feed is dropped. Symmetric positive-definite system solved by conjugate gradients with an incomplete Cholesky preconditioner to a relative residual of 1e-8. The drop sweep is solved at 19 antipad sizes, at 1 A and scaled.

Known limitations

One plane and one rail; no parallel planes, no return rail. The regulator is an ideal edge and the package an ideal node. No Joule heating, so no rise of resistance in hot necks. The via barrel and ball are lumped resistances from their geometry. Mechanism and proportion, not a sign-off number.

Evidence

check-models.js suite IR plane: a plain strip is R_s L / W exactly; one small hole in a strip adds the dipole value 2 pi a^2 R_s / W^2 within 3%; the drop never falls as the antipads grow (Rayleigh monotonicity), and when neighbouring holes touch the core is cut off; the vias carry and the feed supplies the whole current; dissipation equals I times the drop (Tellegen); the necks of the first column and the margins carry all of it; the drop is linear in current; a mirror-symmetric map shares current symmetrically; a very resistive via path forces an even share; the 0.2 mm grid agrees with 0.05 mm cells within 2% in drop and 1% in neck density.

Show one network in six domains at once, and link a post-cursor back to the bit that caused it.

Topology

ABCD cascade: causal lossy line, optional mismatched section, optional open stub, causal lossy line. 50 ohm source and load.

Reference planes

Both ports referenced to a real 50 ohm. No package, no connector, no die. Transport delay de-embedded as an exact integer sample rotation and reported separately.

Equations

• z'(f)=Rs(f)(1+j)+jwL, y'(f)=jw*Cvac*eps_r(f)
• gamma=sqrt(z'y'), Zc=sqrt(z'/y')
• eps_r(f) = Djordjevic-Sarkar wideband Debye, decades 1e4 to 1e13
• A=D=cosh(gamma*l), B=Zc*sinh(gamma*l), C=sinh(gamma*l)/Zc
• S21=2/(A+B/Z0+C*Z0+D)

Units

Hz, s, ohm, V. Loss referenced to a FIXED 8 GHz belonging to the board, not to the symbol rate.

Validity

Single-ended, no crosstalk, CTLE only, ideal terminations. Loss is a budget at one frequency split between two mechanisms, not an arbitrary measured curve. Validity is per measurement, not per page: an impulse response that has not decayed inside its record marks the IMPULSE and PULSE panels and names them; it does not invalidate the S-parameters, and it is not used to infer the eye's accuracy. The eye's accuracy is measured directly instead - every released preset is within 0.35 mV of its value at four times the record.

Numerics

4096-point FFT at 32 samples/UI. Pre-wavefront energy below 1e-5 of the total and falling as the record is refined at fixed bandwidth. Propagation loss meets its budget to 1e-6 dB; |S21| differs from it by up to 5e-3 dB, which is the port mismatch of a lossy line whose Zc is not its nominal z. The tail diagnostic measures |h| at a quarter-record or more from the response PEAK. Measuring a fixed last eighth of the circular record instead reported 3.8462% on a matched lossless line with no reflector anywhere — the sidelobes of a band-limited fractional delay, falling as 1/n, wrapping in behind a peak that sits at sample 0. Impulse exports are dimensionless discrete convolution weights; normalized SBR exports are dimensionless too. The panel converts SBR weights to volts using its transmitted amplitude. Raw and active impulse records share dt and removed transport delay tdBulk; absolute display labels add tdBulk without changing the samples. The early view is a display window, and the full FFT record remains available. Frequency inspection selects the nearest native sample in linear Hz and links S21, S11 and group delay; exported group delay is in seconds. It does not interpolate wrapped phase or rebuild the model.

Known limitations

Not a field solver, not coupled-line, not correlated against measurement. The eye height is the extremal gap between the two transmitted populations over one PRBS7 period at the decision instant — not a percentile, not a BER contour, and not comparable with a compliance eye height.

Evidence

docs/channel-model.md is the contract; every clause has assertions. check-models.js — Causal line (44 assertions): lossless Zc and delay exact, loss budget exact, agreement with an independently derived S21 to 1e-12, pre-wavefront causality with measured convergence, and eps' monotone with eps'' flat. Lab B assembled (60 assertions): the arrival is retained for every preset and both extremes, one sampling phase across four views, populations labelled by transmitted symbol, an ideal channel delivering the full swing with zero errors, and S-parameters unchanged by a rate-only change. mutate.js: nine planted defects each caught by the assertion that claims it.

Say in amps which capacitor bank supplies the load at each frequency, and which two make each peak.

Topology

Five-stage ladder: VRM, bulk, board, package, die. Series R-L between stages, shunt R-L-C at each.

Reference planes

Board and die load nodes on one five-stage ladder; observe either node. Frequency branch-share panels retain unit die excitation.

Equations

• Zout_vrm=R(1+jf/fbw)
• ladder reduction from the VRM end
• M di/dt + R i + vC = -Br I - Bl dI/dt; dvC/dt = diag(1/C)i
• Y(f) v(f) = i(f); Zij = vi / ij
• rail deviation dVi = -sum_j Zij Ij for positive withdrawal

Units

Hz, ohm, A, V, s

Validity

Lumped five-stage RL/series-RLC network with zero initial incremental state. No plane cavity modes or spatial distribution. The browser transient is causal. Droop and overshoot are measured through the record and an exact ring-down until the rail settles, so they do not depend on how long the record is; timestep resolution still matters.

Numerics

420 log-spaced frequency points with nodal transfer impedances. Two-load browser transients use an eight-state causal ladder model and a small matrix exponential with first-order-held sampled currents; analytic raised-cosine derivatives recover inductive voltage. Nominal record 32768 × 200 ps; edge refinement halves dt and doubles sample count at fixed duration. Physical event times are rounded to samples. Signed contributions are solved separately and summed; no repeating-record tail is introduced. The legacy single-load API and explicit test-only periodic option retain FFT convolution for regression comparisons. All board/die complex transfer pairs and full-precision time traces remain exported. Frequency inspection retains nearest-native-Hz semantics. Once both loads are off, each observation continues by free evolution, exact for zero input (one matrix exponential of A × 2 ns), sampled every 2 ns until the combined response stays within 0.1% of its largest excursion for 10 µs or 1 ms has passed; droop and overshoot are taken over record and ring-down, with the time each occurs.

Known limitations

The causal transient starts from zero incremental state and approximates current between samples linearly. A quiet pre-event baseline follows from causality and is not a timestep convergence certificate. Six selected two-load corners and a seeded sample of the control ranges (24 settings in the gate, 240 in the recorded sweep) are compared with an independent causal trapezoidal reference; that is sampled evidence, not proof for every parameter combination. Reported extrema cover the record and the ring-down; a rail still moving after 1 ms is reported as not settled and its droop and overshoot are withheld. The VRM remains a first-order R+jwL teaching model, without compensation, phase margin or nonlinear behavior. The topology has one die and one board load; scalar target impedance remains a single-load heuristic. Frequency branch-current magnitudes can exceed the injected current because phasors circulate. Legacy FFT-only helper results retain periodic-record limitations. The ladder is linear: load currents do not respond to the rail and the regulator never saturates. An excursion above 0.5 V at either node, half of a nominal 1 V core rail, is still reported but flagged as beyond what the model can describe.

Evidence

check-models.js — PDN ladder (21 assertions): DC limit is the resistive path, 5 GHz limit is the die ESL reactance, the biggest peak matches the closed-form VRM-against-bulk resonance, and |Z| agrees with K.cascadeS — a separate code path — to 1e-6 ohm. Lab C transient (N2-4): the reference solver is itself validated against an analytical DC limit — capacitors open, inductors shorted, 7.8 mOhm at the die — which it reaches to under a microvolt from rest; 200 ps and 400 ps are asserted to differ; every requested edge is asserted to be realised exactly; droop is asserted monotone in edge rate and to fall 3.36% across the control. Causal two-load path: tests/check-pdn-multi.js compares six corners at both observation nodes, checks timestep and record extension separately, and exercises closed-form causal/periodic references and targeted numerical faults. Lab C ring-down (11 assertions): with a 10 kHz regulator the die overshoot peaks at 13.8 µs, after the plotted window, and matches the reference run straight through the ring-down (367.512 mV); a four-times-longer record reports the same extremes. tests/check-pdn-domain.js: 24 seeded settings across every control range against the reference, driven with the model’s declared stimulus (240 in the recorded sweep: worst waveform 0.194%, droop 0.120%, overshoot 0.140%), and no reported extreme smaller than one a longer record contains. Lab C large-signal flag (6 assertions): the default (142 mV) and no-die (399 mV) presets are not flagged; a 20 A, 200 ps board load is, at the board, where the independent reference confirms 7.30 V.

Make the current half of a travelling wave visible, and account for where the energy goes.

Topology

As reflection, with variable length and 24 launched waves.

Reference planes

Driver node, load node, and a movable probe along the line.

Equations

• V/I=+Z0 forward, -Z0 backward
• E=Td*int(0.5 v^2/Z0 + 0.5 i^2 Z0)

Units

ps, V, A, ohm, pJ

Validity

Lossless, uniform, no mid-line discontinuity.

Numerics

Trapezoid integration with 900 time intervals and max(220, ceil(64 Td/tr)) spatial intervals, capped at 65536. The energy history uses 121 uniformly spaced times plus finite-edge boundary transition landmarks; straight segments join computed samples. History is cached until physical settings change. Cursor energies are recomputed at the actual cursor time; the residual is shown on a separate aligned scale. Energy integrals begin before the source edge. Energy-history UI updates debounce rapid physical edits, then yield between samples with a generation guard. Pending histories are hidden and omitted from exports; instantaneous calculations remain current. Completed histories use the same sample grid and quadrature as the synchronous model.

Known limitations

Lossless, uniform, no mid-line discontinuity. The energy account is refused rather than reported when it closes to worse than 1%. Across every length and edge the controls allow it now closes to 0.086% or better.

Evidence

check-models.js — Line1D (21 assertions), shared with the reflections panel.

Show why LPDDR6 raised bandwidth by going wider at NRZ rather than faster or to PAM4: the same raw bandwidth carried three ways through one short channel at LVSTL's swing.

Topology

One channel shared by three roads: faster NRZ on 16 pins, PAM4 on 16 pins at half that symbol rate, and NRZ on N pins (24 for LPDDR6) at the LPDDR6 bin rate x 24/N. A causal two-term loss channel plus one echo at a fixed delay in picoseconds.

Reference planes

The receiver's input, before any equaliser unless the one-tap DFE is on.

Equations

• raw bandwidth = 24 x LPDDR6 rate; fast rate = raw/16, PAM4 baud = raw/32, wide rate = raw/N
• loss at a road's Nyquist = L5 (0.35 sqrt(f/5 GHz) + 0.65 f/5 GHz)
• swing = VDDQ RTT/(Ron + RTT) = 0.5 V x 40/80 = 250 mV; PAM4 level spacing = swing/3
• margin = eye - 2 Q sigma, Q = 7, vertically in mV and horizontally in ps

Units

mV, ps, Gb/s, GBd, dB

Validity

Linear channel; LVSTL swing with Ron = RTT = 40 ohm (model choice); one echo; crosstalk and supply noise folded into one rms figure; ideal one-tap DFE when on.

Numerics

Kit channel impulse on a 4096-point grid at 32 samples a symbol; raised-cosine edge of 0.3 UI; PRBS-11 (NRZ) and PRBS-11 pairs (PAM4) superposed over the pulse response; eye openings measured with the kit's eyeContour.

Known limitations

No crosstalk modelled from neighbours, no SSN, no supply noise beyond the rms figure; the same echo on every road; equalisation is either none or an ideal one-tap DFE; the PAM4 receiver is ideal.

Evidence

check-models.js - LPDDR6 page (a perfect channel opens NRZ to the full swing and PAM4 to a third of it; every road carries the same raw bandwidth; 16 wide-road pins reproduce the faster-NRZ road exactly; each road's loss is the law at its own Nyquist; more loss never opens an eye; the echo lands at its delay over the UI; DBI never sends more ones than it saves and never leaves a group above half ones; the termination energy of a 1 is VDDQ^2/(Ron+RTT) x UI).

Compare NRZ and PAM4 on the same channel at the same data rate: PAM4 halves the Nyquist frequency and so meets less loss, and pays for it with a third the eye height.

Topology

Two full chains, identical except for the alphabet. Each runs K.channelImpulse at its own Nyquist loss, the shared CTLE at a fixed boost, and the shared DFE with a fixed tap count. NOT an ideal-level comparison.

Reference planes

Transmitter output.

Equations

• loss_NRZ = lossPerGHz * rate/2, loss_PAM4 = lossPerGHz * rate/4
• level spacing penalty = 20*log10(3) = 9.54 dB at equal total swing
• h = ctle(channelImpulse(loss, sps, nfft)); y = applyDFE(conv(levels, h), ...)

Units

dB, V

Validity

A controlled comparison of two alphabets on one loss law, not a system margin. Fixed CTLE boost and fixed DFE taps for both, deliberately, so the comparison is about the alphabet. No adaptation, no jitter, no crosstalk, ideal terminations.

Numerics

FFT channel at 32 samples/UI, minimum phase by real cepstrum; seeded symbol sequence. The 9.54 dB level-spacing figure is exact arithmetic and is checked separately from the chain.

Known limitations

The 20*log10(3) level-spacing penalty is a fact about amplitudes and is exact. Everything else on the panel is the output of a numerical channel, and the two should not be read with the same confidence.

Evidence

check-models.js — DFE and Convergence suites cover the chain's parts: exact cancellation with known symbols, the half-open tap window, gain-aware slicing for PAM4 (M2-7), and grid independence of the channel. The 9.54 dB figure is in check-numbers.py.

Show why PCIe 4.0 and 5.0 links equalise at run time: on a channel built from the four places the loss budget goes, what each transmitter preset and the reference receiver's CTLE and limited DFE make of the eye, and which preset a Phase 2-3 sweep would keep.

Topology

CPU package, motherboard trace, CEM connector and add-in card in series; package, connector and card at TI's allocation for the generation, the board at the reader's length and laminate. A 3-tap transmitter FIR from the P0-P9 table at 800 mV full swing; a one-zero, two-pole CTLE at the reference DC gains; a 2-tap (Gen 4) or 3-tap (Gen 5) DFE with per-tap limits.

Reference planes

The transmitter pins to the receiver's slicer, after CTLE and DFE.

Equations

• IL(f) = L_N (0.35 sqrt(f/fN) + 0.65 f/fN), L_N the sum of the four segments at Nyquist
• board loss at 8 GHz = (loss at 16 GHz) x (0.35 sqrt(0.5) + 0.65 x 0.5)
• launched pulse = c-1 p(t + UI) + c0 p(t) + c+1 p(t - UI)
• DFE tap k = clip(A q(s + kUI), +/- limit_k)
• worst-case eye at s = 2 (A q(s) - sum over k != 0 of |A q(s + kUI) - d_k|)

Units

dB, GHz, in, mV, UI

Validity

A linear, time-invariant channel with the site's two-term loss law and no reflections; a noiseless receiver. Mechanism and proportion: which preset helps, by roughly how much, and when none can.

Numerics

Minimum-phase channel impulse at 32 samples per UI on a 4096-point FFT; one pulse response per channel, the CTLE applied to it for each reference setting (linear, so in either order); the eye is peak distortion over the whole pulse, its sampling point the tallest within a UI of the pulse peak, its width the span about that point where the height is at least 15 mV.

Known limitations

The CTLE is the site's one-zero, two-pole filter at the reference DC gains, not the Base specification's pole and zero placement (Gen 5's has four poles and two zeros). No noise, jitter, crosstalk or reflections, so via stubs and connector discontinuities are not in it. The eye is the worst case of any pattern, not an extrapolation to 1e-12, and the receiver's CTLE is chosen for the tallest eye, where a real one also weighs noise. Not SigTest, Seasim or any compliance flow.

Evidence

check-models.js suite PCIe equalisation: P4 leaves the pulse exactly as it was; the FIR, run on a pattern with no channel, launches every preset's preshoot and de-emphasis to 0.1 dB, and no pattern exceeds the unshaped swing; peak distortion matches hand arithmetic for a three-cursor pulse with no DFE, an unlimited DFE and a DFE clipped at 20 mV; the DFE never removes pre-cursor; a lossless channel gives the full 800 mV; more board never opens the eye; 400 bits of data never cross the worst-case eye; the sweep keeps its best preset; the same loss at Nyquist gives the same eye at 16 and 32 GT/s; no DFE tap exceeds its limit.

Show a capacitor bank's impedance and where mounting inductance takes over.

Topology

N parallel RLC branches against a plane.

Reference planes

One port.

Equations

• Z=R/N+j(w*L/N-1/(w*C*N))

Units

Hz, ohm

Validity

Lumped; no plane modes; no package.

Numerics

Direct complex evaluation.

Known limitations

Lumped; no plane modes; no package.

Evidence

check-models.js — PDN (RLC limits and damping).

Show where the return current of a signal via that changes reference goes: a wave between the planes when nothing carries it, and how much a stitching via or capacitor, and its distance, changes the noise at another via.

Topology

One rectangular plane pair, 100 x 60 mm, 0.2 mm apart, Dk 4 at 1 GHz, open edges. The signal via's return current is a current source between the planes; stitching vias and four mounting holes short the planes; between GND and PWR they are series R-L-C capacitors instead.

Reference planes

The voltage between the two planes, at every cell and at the victim via.

Equations

• TMz: dEz/dt = (dHy/dx - dHx/dy - sigma*Ez - Jp - Jz)/eps_inf, dHx/dt = -(dEz/dy)/mu0, dHy/dt = (dEz/dx)/mu0
• Debye: tau*dJp/dt + Jp = eps0*dEps*dEz/dt, fp = 2.8 GHz, dEps = 0.2
• V = -Ez*h; source Jz = I(t)/dx^2, I(t) a Gaussian edge; via: Ez = 0 in its cell
• capacitor: L di/dt + R i + q/C = V, dq/dt = i
• Z21(f) = FFT(dV_victim/dt) / FFT(dI/dt)
• f_mn = c/(2*sqrt(Dk)) * sqrt((m/a)^2 + (n/b)^2)

Units

mm, ns, ps, mA, mV, ohm, GHz

Validity

A plane pair much thinner than a wavelength, so the field between the planes is uniform through the gap, up to about 6 GHz, where a 0.5 mm cell is still 24 cells per wavelength.

Numerics

Yee grid of 0.5 mm cells (200 x 120), time step 95% of the 2D Courant limit (2.19 ps), 20 ns record. Magnetic-wall edges. Debye polarisation by an auxiliary current, averaged across the step. Lumped capacitor with its resistance semi-implicit. Float32 fields. Transfer impedance from the derivative records, the last 30% tapered.

Known limitations

One plane pair: no coupled cavities, no antipads, no via barrels above or below the pair. A via is one 0.5 mm cell. Edges do not radiate. The signal's own line is not modelled; its return current is imposed. Loss lumped into one Debye pole and a conductivity, within 15% of a laminate tan d 0.02 plus plane copper from 0.3 to 6 GHz. Mechanism and proportion, not a sign-off number.

Evidence

check-models.js suite Plane cavity: with no vias and no loss the resonances land on the closed-form f_mn within 0.5%; the discrete field energy after a pulse is conserved within 0.01%; with no DC path the planes charge at Q/C; nothing reaches the victim before the fastest wave; swapping source and victim gives the same waveform; a resonance rings down with Q = 1/tan d of the stated medium; an electrically small board with one capacitor resonates at 1/(2 pi sqrt(L C_plane)); noise at the victim falls as a stitching via comes closer, and rises with a capacitor's mounting inductance, a via beating every capacitor.

Show what a marked capacitance is worth at an operating point, and how much of the answer the derating uncertainty owns.

Topology

One capacitor: ESR(f) in series with ESL_part + L_mount in series with Ceff. No neighbours, no plane.

Reference planes

One port, at the capacitor terminals as mounted. Nothing beyond the mounting loop.

Equations

• Z=ESR(f)+j(w*Ltot-1/(w*Ceff))
• Ceff=cNom*retained
• SRF=1/(2*pi*sqrt(Ltot*Ceff))
• L_mount=length*(mu0/pi)*acosh(s/2r)
• ESR=esrMin*cosh(ln(f/fMin)/2)

Units

Hz, ohm, F, H

Validity

Lumped R+L+C. Not valid above the part body's first structural resonance. The retained fraction is an INPUT - this panel does not know your derating and will not guess it.

Numerics

Closed form at every frequency. The band is the exact envelope over the capacitance range, not a two-endpoint min/max.

Known limitations

No temperature coefficient on ESR, although one is measured to exist at high frequency. No mutual coupling to neighbouring parts. The ESR shape between its anchors is illustrative.

Evidence

check-models.js — Real capacitors (11 assertions): SRF scales exactly as one over root C independent of L and ESR, the two-term ESR equals the closed form esrMin*cosh(ln(f/fMin)/2), reactance is zero at SRF so |Z| there is ESR(SRF), the marked and derated curves converge above resonance and differ by exactly the retained fraction below it, the band provably contains the operating point at every frequency, and a zero retained fraction is refused rather than drawn.

Show how a step reflects between two mismatched ends, and why the ringing decays at the rate it does.

Topology

Ideal step source with series Rs, one uniform lossless line of delay Td, one resistive or open load.

Reference planes

Driver output node and load node. No package, no connector.

Equations

• Gs=(Rs-Z0)/(Rs+Z0)
• GL=(RL-Z0)/(RL+Z0)
• a0=Vs*Z0/(Rs+Z0)
• V(x,t) by superposition of 7 launched waves

Units

ps, V, ohm

Validity

Passive terminations. Lossless: late-time amplitudes are optimistic.

Numerics

Closed-form lattice sum. The edge is a CUBIC SMOOTHSTEP, s^2*(3-2s), centred on t = 0 and spanning tr from 0 to 1 — not a raised cosine, which the contract and the module header both used to claim. The two differ by at most 1% pointwise, but the rise-time convention differs: a cubic smoothstep's 10-90% time is 0.608*tr where a raised cosine's is 0.590*tr.

Known limitations

tr is the full 0-100% support of the smoothstep, not a 10-90% time. Multiply by 0.608 to compare with a datasheet 10-90% figure. Lossless, so late-time amplitudes are optimistic.

Evidence

check-models.js — Line1D (21 assertions): Ohm's law at the load and Kirchhoff at the source hold to 1e-12 at every instant; energy balances across five terminations.

Show where the return current under a trace flows in its reference plane, from the DC spread between the vias to the high-frequency band under the trace, after a step in time, and around a slot or through a capacitor that bridges it.

Topology

One copper plane, 60 x 40 mm, 35 um thick, under one trace 0.2 mm wide at 0.2 or 1.5 mm. The trace runs from a driver via to a load via along a Manhattan route; its current is imposed, 1 A. Slots are cells removed; a stitching capacitor is a series R-L-C between two cells across a slot.

Reference planes

The sheet current in the plane at every cell, the loop impedance of trace and return, and the share of the return within 2 mm of the trace across the middle of its longest run.

Equations

• every plane bar: V = Zs I + jw (L I) + jw M I_trace, Zs = rho k coth(k t), k = (1 + j)/delta
• every mesh of the plane: sum of V = 0; bar currents I = I_p + C psi + sum p_c I_c
• partial inductance of two parallel thin tapes: (mu0/4pi)/(w1 w2) * sum over 16 corners of F(u, v, z), d4F/du2dv2 = 1/R
• capacitor: Z = R + jwL + 1/(jwC)
• Z_loop = sum over every branch of I V (Tellegen), R = sum R |I|^2
• step: backward Euler, (C^T (R + L/dt) C) psi_n+1 = (C^T L C / dt) psi_n - C^T R I_p, from the inductive limit at t = 0+

Units

mm, nH, mohm, Hz, s

Validity

Quasi-static: the plane is much smaller than a wavelength (60 mm against 1.5 m in FR-4 at 100 MHz), so currents are solved without propagation delay or radiation, from 10 Hz to 100 MHz.

Numerics

2,400 square cells of 1 mm. Unknowns are mesh currents on the cell corners, tied across every missing bar. Plane-to-plane partial inductances are a Toeplitz kernel, applied by FFT convolution. Complex symmetric system solved by conjugate-orthogonal conjugate gradients to a relative residual of 1e-7, preconditioned by the sine-transform inverse of the slot-free operator. 43 frequencies (E6 series); 25 backward-Euler steps from 10 ns to 10 ms.

Known limitations

One plane, no second reference and no other planes. The trace current is imposed rather than solved as a transmission line; the vias are lumped partial inductances. The band under the trace is drawn no narrower than one 1 mm cell, although the inductance converges (0.5 mm cells agree within 0.5%). The capacitor is lumped, its mounting loop not coupled to the plane. The step uses the DC sheet resistance. Mechanism and proportion, not a sign-off number.

Evidence

check-models.js suite Return path: under a long straight trace at high frequency 50% and 80% of the return lie within +-h and +-3h, the image-theory Lorentzian; the loop inductance matches the image-theory rectangle; the DC current depends only on the vias, not the route; the return crossing the middle is the whole current at every frequency; the bilinear and power forms of the loop impedance agree; L never rises and R never falls with frequency; a slot never lowers the high-frequency inductance or the DC resistance; the step starts at the inductive limit and ends at DC; a capacitor across a slot carries nothing at 1 kHz and most of the return well above its resonance.

Show what passivity, reciprocity and causality each assert, separately.

Topology

Through-section and stub networks.

Reference planes

Two 50 ohm ports.

Equations

• exact ABCD of a mismatched through-section and an open stub

Units

Hz, dB

Validity

Lossless unless stated; two-port only.

Numerics

Closed form.

Known limitations

Lossless unless stated; two-port only.

Evidence

check-models.js — Networks (passivity, and reciprocity checked as a separate property).

Tie the edge in time to the envelope in frequency.

Topology

Trapezoidal clock, one edge rate, one duty cycle.

Reference planes

Driver output.

Equations

• |An| proportional to |sinc(n*pi*tau/T)|*|sinc(n*pi*tr/T)|

Units

Hz, s, dB

Validity

Ideal trapezoid; no channel.

Numerics

Closed form harmonics.

Known limitations

Ideal trapezoid; no channel.

Evidence

check-models.js — Spectrum (a 50% duty square wave has no even harmonics).

Show what USB's mandatory spread-spectrum clocking asks of the receiver: how far the sweep moves the data, how closely a type-2 clock-recovery loop follows it for a given bandwidth and damping, and why the sweep's slope, not its depth, sets the lag.

Topology

A down-spread clock, a triangle or a legal profile that ramps at the 1250 ppm/us limit and holds, driving the site's second-order type-2 CDR loop (K.cdrLoop).

Reference planes

The data's phase at the receiver, against a clock at the sweep's average rate; the recovered clock; their difference at the decision.

Equations

• x(t) = integral of (df/f - mean) dt, the data's time error against the average-rate clock
• H(s) = (2 zeta wn s + wn^2) / (s^2 + 2 zeta wn s + wn^2)
• residual r = (1 - H) x, harmonic by harmonic over one SSC period
• steady ramp lag of a type-2 loop = (ramp rate) / wn^2

Units

ppm, kHz, MHz, ps, UI

Validity

A linear loop in its steady state against a periodic sweep. Exact for that loop at the 4096 samples per period used.

Numerics

One SSC period sampled 4096 times; the phase is the trapezoid integral of the profile, mean removed; one FFT, the complex 1 - H at each harmonic, one inverse FFT.

Known limitations

A linear, noiseless loop: no phase-detector gain variation, no bang-bang behaviour, no slew limit inside the loop, and no other jitter. The loop's natural frequency is reader-set; the specification states tolerance masks, not a loop. Not a compliance test.

Evidence

check-models.js suite SSC tracking: a triangle of plus or minus A moves the data A T / 4 peak to peak (189 UI at Gen 2, 104 at Gen 1 and 30 kHz); mid-ramp the loop lags by the ramp rate over wn^2, equally at plus and minus half the offset; a time-stepped loop against the triangle's phase written out by hand settles to the same peak-to-peak as the Fourier answer at three bandwidth and damping settings; no spread leaves nothing; a faster loop never leaves more; H tends to 1 below fn and 0 above it; the steep profile slews at 1250 ppm/us and the triangle at 4 A fm.

Show ground bounce as v=L di/dt across a shared return.

Topology

N drivers sharing one return inductance.

Reference planes

Die-side ground against board ground.

Equations

• v=L*di/dt
• peak slope = (pi/2)*dI/tr for a raised-cosine edge

Units

A/s, H, V

Validity

Single lumped shared inductance; no mutual coupling between returns.

Numerics

Closed form; peak rather than mean slope reported.

Known limitations

Single lumped shared inductance; no mutual coupling between returns.

Evidence

check-numbers.py — the di/dt and mean-slope figures are recomputed from first principles.

Show what a TDR reports for a channel built from a few sections, against what the channel is: where features appear, how the edge limits resolution, and how loss and masking distort the reading.

Topology

A 50 ohm launch, one or two lumped vias (shunt C or series L), a trace, a section at another impedance, a second trace, and a matched, open, shorted or resistive load.

Reference planes

The instrument's reference plane, at the start of the launch line; distance is measured from it.

Equations

• Gamma(f) from the cascade's ABCD: Zin = (A ZL + B)/(C ZL + D), Gamma = (Zin - Z0)/(Zin + Z0)
• rho(t) = integral of the S11 impulse response against a raised-cosine edge of 10-90% rise t_r
• Z(t) = Z0 (1 + rho)/(1 - rho), the naive single-reflection reading, with no layer peeling
• distance = round-trip time x v / 2, at 170 ps/in

Units

ohm, ps, in, pF, nH, dB/in

Validity

TEM sections with the kit's lossy-line material (Dk 4.03, two-term loss law, complex Zc); lumped vias; a matched 50 ohm instrument; the edge is a raised cosine.

Numerics

S11 on an 8192-point grid at 1 ps (an 8.2 ns record), inverse FFT, O(N k) edge integration; time zero at the edge's 50% point.

Known limitations

Single-ended only; no instrument or probe parasitics, no cable loss before the reference plane, no layer peeling, no dispersion beyond the loss law.

Evidence

check-models.js — TDR page (a matched line reads Z0; an open reads +1 and a short -1; a long section reads its own impedance; a short one reads shallower; a feature appears at its round trip; the dip area equals Z0 C/2 and the bump area L/(2 Z0) for any edge; two features merge below the edge and separate above it; a lossy line reads rising; the fast integration equals the direct convolution).

Show what each way of ending a line buys and costs on the same driver, line and data: the waveform at the far end, at a second receiver part-way along and at the driver pin, and the average power each scheme burns in its termination and in the driver.

Topology

An ideal source behind the driver's impedance, with a series resistor for series termination; one uniform lossless 50 ohm line, split at an optional second receiver; a 1 pF input capacitance at each receiver; at the far end nothing, R to ground, a Thevenin pair to the 1.2 V rail and ground, R + C to ground, or R to the rail inside the pin (on-die, to VDDQ). A board-mounted terminator can sit past a 5 mm stub of the same line and a 2 nH via.

Reference planes

The driver pin, the second receiver and the far-end pin; the terminator's own node behind a stub. Thresholds at 35% and 65% of the rail.

Equations

• line end: v = 2 a(t) + Z0 i_in, a(t) = the wave leaving the other end at t - Td (Bergeron, exact for a lossless line)
• capacitor: i(n+1) = (2C/dt) v(n+1) - [(2C/dt) v(n) + i(n)] (trapezoidal companion)
• inductor: i(n+1) = (dt/2L) v(n+1) + [i(n) + (dt/2L) v(n)]
• Thevenin pair: R1 = Rt / b, R2 = Rt / (1 - b), so R1 || R2 = Rt and the bias is b Vdd
• power: i^2 R in every resistor, from the solved waveforms, averaged over the measured bits
• edge spread: the far end's mid-swing crossings, each against when its edge was sent; max - min

Units

ps, ns, V, ohm, pF, nH, mW

Validity

Lossless lines, linear terminations and an ideal driver behind a fixed resistance. The receiver is a capacitance and two thresholds.

Numerics

Nodal analysis at each time step with a matrix factored once; 20 samples per edge and at least 8 per line section, at most 60,000 steps (20,000 for the five schemes that only feed the cost chart). Line delays rounded to whole steps. The record starts from the DC operating point; a clock starts from its own average, as a clock that has been running does; the first two bits are left out of every measurement.

Known limitations

No line loss, so late-time ringing is optimistic; no driver nonlinearity, slew control or supply bounce; on-die termination is always on, not gated per burst; the receiver has no clamp diodes, so an unterminated far end's overshoot is not limited. Mechanism and proportion, not a sign-off number.

Evidence

check-models.js suite Termination: a matched load returns nothing and the far end is the launched wave delayed by Td exactly; the waveforms agree with the superposition model K.line1D at both ends for five resistive terminations; series termination seen from a tap sits at Vdd/2 for 2(Td - t_tap); settled levels are the resistive divider and Millman's theorem; AC termination tends to a resistor as C grows and to an open as it vanishes, and charges with (Rs + Rt) C; an LC tank rings at 2 pi sqrt(LC); charging the line through a matched source stores half the energy and burns the other half for a fast edge, less for a slow one; the energy account closes to rounding for lines and resistors, and with capacitors to a residual that halves with the step; resistive terminations put every edge in the same place on random data while an AC terminator moves them on data far more than on a clock.

Report what a Touchstone 1.0 two-port file contains, and whether this reader can trust it.

Topology

No model. It parses a file and computes properties of what it read.

Reference planes

Whatever the file's own reference planes are — the reader cannot know and does not guess.

Equations

• sigma_max(S) = sqrt( largest eigenvalue of S^H S ), over the FULL complex 2x2
• T = sum |Sij|^2, D = |det S|^2, sigma_max = sqrt( (T + sqrt(max(0, T^2 - 4D))) / 2 )
• IL = -20*log10(|S21|)
• reflection in dB = 20*log10(|S11|); return loss = -20*log10(|S11|)

Units

Hz after conversion from the file's own unit; dB; linear S

Validity

Touchstone 1.0, two-port, S-parameters, MA/DB/RI format, Hz through GHz. Strictly ascending non-negative frequencies. Values validated AFTER unit and format conversion, because a finite 1e308 becomes infinite once multiplied by 1e9.

Numerics

Exact arithmetic on the file's own numbers. No interpolation, no renormalisation, no extrapolation.

Known limitations

An INSPECTOR, not an importer. It cannot feed the channel lab, because that needs renormalisation to the model's reference impedance, interpolation onto its frequency grid and a DC extrapolation — three pieces of numerical work with three error budgets, none written. Does not support Touchstone 2.0 keywords, noise data, ports other than two, Y/Z/H/G parameters, per-port reference impedances, or any repair of a malformed file. Passivity is evaluated only at the frequencies the file contains: it establishes nothing about the gaps between samples, about causality, about measurement quality, or about fitness for a transient transform.

Evidence

check-models.js — Touchstone (30 assertions): refuses a 2.0 file, a non-2-port file, a missing option line, a wrong reference impedance, descending or negative frequencies, and values that overflow after conversion. Accepts MA, DB and RI and agrees between them to 1e-9. Passivity (N1-3): sigma_max(S) is computed from the full complex matrix and cross-checked against power iteration -- a different algorithm -- over 300 random complex matrices to 1e-9, plus four checked-in .s2p fixtures whose true singular values were computed independently: a unitary asymmetric network the retired |S11 +/- S21| shortcut called active at 1.414, an active one it called passive at 0.5, a non-reciprocal isolator it reported as 0.000, and a port-symmetric lossy case where the shortcut was correct and still is. The degenerate case that makes the discriminant negative in floating point is asserted by name.

Show how much die edge a die-to-die bandwidth needs on a standard or an advanced package, at each UCIe data rate, and the power it burns.

Topology

No channel: arithmetic on the UCIe Consortium's published key metrics for UCIe-S (110 um reference pitch) and UCIe-A (45 um).

Reference planes

Die edge, in the consortium's shoreline terms.

Equations

• edge = bandwidth / shoreline
• shoreline(r) = shoreline(32 GT/s) * r / 32 for r <= 32 GT/s; table values at 48 and 64
• power = bandwidth * 8 * energy per bit
• t_round = 2 * reach * 6.7 ps/mm

Units

TB/s, GB/s/mm, mm, GT/s, pJ/b, W, ps

Validity

The consortium's reference pitches and its energy targets. Shoreline counts both directions together, as the module sizes in C-76 show, so the bandwidth is the total of both directions.

Numerics

Direct evaluation at the eight rates the standard defines.

Known limitations

Energy figures are targets, not measurements; no figure exists for UCIe-S at 24 GT/s, so a range is shown. At 8, 12, 16 and 24 GT/s the shoreline is scaled from the 32 GT/s figure, not read from the table, and the readout says so. No crosstalk, skew, supply or channel model. The round trip assumes a dielectric constant near 4.

Evidence

check-models.js suite UCIe shoreline: the linear scaling reproduces the table's own 4 GT/s figures, the advanced package needs less edge than the standard one at every rate, edge falls with rate, power is bandwidth times energy, and malformed inputs are refused. check-numbers.py recomputes every figure the prose states.

Show how hot a hybrid-bonded UCIe-3D interface runs: power per square millimetre of bonded area against bond pitch and activity, against a heat budget.

Topology

No channel: arithmetic on the consortium's two published UCIe-3D targets (C-71, C-102), at 9 and 1 um bond pitch.

Reference planes

The bond layer between two dies bonded face to face.

Equations

• density(p) = 4000 * (9/p)^kD GB/s/mm2, kD = ln(75)/ln(9)
• energy(p) = 0.05 * (p/9)^kE pJ/b, kE = ln(5)/ln(9)
• power density = density * 8 * energy * 1e-3 * activity W/mm2
• reference budget = 700 W / 814 mm2 (C-103, C-104)

Units

um, GB/s/mm2, pJ/b, W/mm2, TB/s, W, mm2

Validity

Exact at the two published points; between them a power law through both, which is an interpolation. Pitch limited to the 1 to 9 um the targets cover.

Numerics

Closed form, evaluated on 81 points across the pitch range.

Known limitations

The figures are consortium targets, not measurements. Full activity is a worst case. The budget is one product's average and over-states its die, because module power includes memory; the interface's heat adds to the logic's own. No thermal spreading, no hot spots, no power-delivery model.

Evidence

check-models.js suite UCIe-3D heat: the two published targets give 1.6 and 24 W/mm2, power is proportional to activity and area, finer pitch raises density and power density and lowers energy per bit, the interpolation passes through both published points, the activity cap times full power equals the budget, units check (GB/s x 8 x pJ/b = mW), and out-of-range inputs are refused.

Show whether a UCIe wire needs a receiver termination: when echoes settle before the mid-bit sample, and when they do not.

Topology

One 50 ohm line, 6.7 ps/mm, from a resistive driver to a receiver that is open or terminated in 50 ohm, with an optional series resistance per mm.

Reference planes

The receiver input, sampled at the centre of each bit.

Equations

• lossless: v_rx(t) = sum_k (b_k - b_k-1) * step_line(t - k*UI), step_line from K.line1D: waves a0*(GL*GS)^m
• resistive: Z = R' + jwL', Y = jwC', gamma = sqrt(ZY), Zc = sqrt(Z/Y), L' = Z0*tpd, C' = tpd/Z0
• V_rx/V_s = 1 / (A + B/ZL + Rs*C + Rs*D/ZL), A = D = cosh(gamma*l), B = Zc*sinh(gamma*l), C = sinh(gamma*l)/Zc
• t_round = 2 * L * 6.7 ps/mm

Units

ps, mm, ohm, fraction of settled swing

Validity

Exact for the line as modelled: lossless by the lattice of reflections, resistive by the frequency-domain telegrapher solution, with a raised edge of 30% of a unit interval.

Numerics

Lossless: superposition of closed-form step responses over a twenty-bit pattern, 80 reflection terms. Resistive: FFT of the source pattern, record long enough for echoes to fall below 1e-6, at least 32 samples per unit interval.

Known limitations

No pad, ESD or receiver capacitance, no crosstalk, no equalization. Resistance is constant with frequency (no skin effect), which suits thin, DC-resistance-dominated interposer traces. Z0, the edge and 6.7 ps/mm are choices, not UCIe figures. A mechanism, not a sign-off margin.

Evidence

check-models.js suite UCIe echo: a matched receiver and a matched driver each give no echo, the first arrival at an open receiver is 2*Z0/(Rs+Z0), a very short line behaves as a lumped load, the long-run level settles to the resistive divider; and for the resistive line, an independent frequency-domain solver reproduces the lattice at vanishing resistance, the first arrival is attenuated by exp(-R l / 2 Z0), and a terminated wire settles to Z0/(Z0+Rs+R l). The shared solver K.line1D is checked by the Line1D suite.

Show where a UFS link's power goes between transfers: what staying in STALL and dropping to HIBERN8 each cost per transfer, the idle at which sleeping starts to pay, the latency the wake adds, and the rail step a burst draws when it starts.

Topology

Transfers of a set size over two lanes at HS-G4 or HS-G5 after 8b10b, an idle gap between them, and a policy: wait in STALL, or go to HIBERN8 after a threshold and wake before the next transfer. The rail is a regulator, a bulk capacitor, board decoupling and a package into the die.

Reference planes

The PHY's supply, as power by state; the die end of the rail for the droop.

Equations

• t_burst = size x 8 / (rate x 2 lanes x 0.8)
• E = P_burst t_burst + P_stall min(gap, theta) + P_h8 max(0, gap - theta) + [gap > theta] P_wake t_wake
• break-even idle = theta + P_wake t_wake / (P_stall - P_h8)
• rail: v(t) = IFFT[ Z_PDN(f) x FFT[ i(t) ] ]

Units

us, ms, mW, nJ, uJ, mV

Validity

A piecewise energy account with fixed power per state, and a linear rail.

Numerics

The account is closed form. The rail is K.pdnTransient on a 32 us record at 2 ns, of which the first 8 us are shown, long enough that the circular transform does not wrap the regulator's recovery onto the step.

Known limitations

The state powers (96, 30, 0.25 and 30 mW for burst, STALL, HIBERN8 and waking) and the rail's parts are illustrative: M-PHY's are in the members-only specification and a PHY's own figures in its datasheet. Only the gear rates and the wake-time range rest on the claim ledger. No SYNC or PREPARE overhead, no UniPro framing, no entry time for HIBERN8, and the wake is drawn at STALL's power. The lesson is the shape of the trade and the break-even's dependence on the wake, not any milliwatt.

Evidence

check-models.js suite UFS burst: the account equals the integral of power over the timeline; the policies' energy curves cross exactly at P_wake t_wake / (P_stall - P_h8) for three wake times; with no idle both policies cost the same; sleeping adds exactly the wake time and STALL adds none; average power never rises with the gap; the rail droop scales with the current step, vanishes without one and is still before the step; the burst time is the transfer over two lanes after 8b10b.

Show how a UI is consumed by contributions that are not all the same kind.

Topology

A budget, not a circuit.

Reference planes

Controller pin to DRAM pin.

Equations

• UI_ps = 1e6 / rate_MTps (the control is a TRANSFER rate in MT/s)
• left_ps = UI_ps - sum(terms) (a linear, worst-case stack; training scales the tWCK2DQ term by 0.25)

Units

ps

Validity

ILLUSTRATIVE — the contributions are representative magnitudes, not JEDEC values. Training gain is a labelled model, not a specification.

Numerics

Exact arithmetic on the budget terms. At 8533 MT/s, UI = 1e6/8533 = 117.2 ps, which is what the page states. The rate control offers bins from 3200 to 10700 MT/s; 9600 and 10700 are vendor parts, not JESD209-5B bins.

Known limitations

Until 18 Oct 2026 the contract said the terms were summed as an RSS; the code has always added them linearly, and the contract now says so. The contract previously wrote UI = 1/(2*rate), which is the formula for a clock frequency rather than a transfer rate and would have given 58.6 ps. The code was always right; the contract was not. The budget split itself is illustrative — the terms are plausible magnitudes, not a sourced allocation.

Evidence

check-numbers.py — the UI at 8533 MT/s is recomputed. The allocation is not sourced; see docs/claims.md.

Show that where supply noise enters decides whether the loop removes it.

Topology

First-order PLL, three injection points: VCO, reference, output buffer.

Reference planes

Clock output.

Equations

• VCO noise high-passed at the loop bandwidth; reference noise low-passed; buffer noise uncorrected

Units

Hz, V, s

Validity

ILLUSTRATIVE topology — a first-order loop, not a solved PLL, and a linear small-signal sensitivity. What IS independently checked is the behaviour that matters: the three injection points are treated oppositely, and the units are dimensionally correct.

Numerics

Closed-form transfer functions.

Known limitations

ILLUSTRATIVE topology — a first-order loop, not a solved PLL, and a linear small-signal sensitivity. What IS independently checked is the behaviour that matters: the three injection points are treated oppositely, and the units are dimensionally correct.

Evidence

check-models.js — PSIJ suite. The assertions cover units and the three transfer paths; they do not validate the loop order.

Show where a rectangular cavity's first modes land and that position matters.

Topology

Rectangular plane pair, open edges, ideal conductors.

Reference planes

Between the two planes.

Equations

• fmn=(c/(2*sqrt(Dk)))*sqrt((m/a)^2+(n/b)^2)

Units

Hz, m

Validity

ILLUSTRATIVE — solid rectangular planes only. Antipads, splits and cutouts perturb every mode.

Numerics

Closed-form mode frequencies.

Known limitations

ILLUSTRATIVE — solid rectangular planes only. Antipads, splits and cutouts perturb every mode.

Evidence

check-numbers.py — the mode frequencies are recomputed from the formula.

Turn a ripple budget and a current step into an impedance line, and show it against a load spectrum.

Topology

None — this is one division.

Reference planes

The point the ripple is specified at.

Equations

• Ztarget=(Vdd*ripple)/Istep

Units

V, A, ohm

Validity

ILLUSTRATIVE — the impedance division is exact arithmetic, but the current spectrum beside it is synthetic and representative, not measured die demand. Assumes a load independent of the rail.

Numerics

Exact arithmetic.

Known limitations

ILLUSTRATIVE — the impedance division is exact arithmetic, but the current spectrum beside it is synthetic and representative, not measured die demand. Assumes a load independent of the rail.

Evidence

check-numbers.py recomputes the worked budget. The current spectrum is not sourced.

Show the shape of a regulator's recovery and that release is its own event.

Topology

First-order loop response to a current step and release.

Reference planes

Regulator output.

Equations

• tau=1/(2*pi*fc)

Units

s, V

Validity

ILLUSTRATIVE — a real loop is not single-pole; order, damping and peaking change the shape.

Numerics

Analytic first-order response.

Known limitations

ILLUSTRATIVE — a real loop is not single-pole; order, damping and peaking change the shape.

Evidence

Not independently verified. The time-constant arithmetic is checked by check-numbers.py.