PCIe 4.0 vs 5.0: Loss Budget, Tx Presets, Link Equalization

At a glance

PCIe 4.0 vs PCIe 5.0: what is the difference?

PCIe 5.0 (2019) doubled PCIe 4.0’s (2017) 16 GT/s to 32 GT/s with the same NRZ signalling and 128b/130b coding (C-125, C-137). The unit interval halved from 62.5 to 31.25 ps and the Nyquist frequency doubled from 8 to 16 GHz. The commonly quoted channel budget grew from 28 to 36 dB (C-6a, C-6b), the reference receiver’s decision feedback equaliser (DFE) grew from 2 taps to 3 (C-138), and Gen 5 added optional modes that shorten link training (C-140). The side-by-side table has Gen 3 as well.

How fast are PCIe 4.0 and PCIe 5.0?

After 128b/130b coding, PCIe 4.0 carries 1.97 GB/s per lane in each direction and PCIe 5.0 3.94 GB/s. That makes 7.88 and 15.8 GB/s on an x4 SSD link, and 31.5 and 63.0 GB/s on an x16 slot, twice that counting both directions: 126 GB/s for a PCIe 5.0 x16 slot. GT/s counts transfers on the wire; GB/s here is data after the coding. The PCIe bandwidth table on the PCIe 6.0 page covers every generation from 1.0 to 7.0.

What is the PCIe 5.0 loss budget?

About 36 dB at 16 GHz end to end, against about 28 dB at 8 GHz for PCIe 4.0 (C-6a, C-6b). One Texas Instruments layout note splits the Gen 5 figure as 9 dB for the CPU package, 16 dB for 9 in of high-loss motherboard trace, 1.5 dB for the slot connector and 9.5 dB for a 4 in add-in card, and asks for another 4 to 5 dB of margin against crosstalk at Gen 5 (C-134). The budget diagram draws Gen 3 to Gen 5 to scale.

How long can a PCIe 5.0 trace be?

It depends on everything else in the channel and on the laminate. TI’s example allots 16 dB to 9 in of high-loss motherboard trace (C-134), and its own materials table puts 1 in of trace at 16 GHz between 0.336 dB on Megtron 6 and 1.844 dB on a tetra-functional FR-4 (C-141). So 16 dB is about 9 in on the worst of those and several times that on the best, before vias, breakout and connectors take their share. Past that you need a lower-loss laminate or a repeater: PCIe 4.0 already called for a redriver or retimer on longer channels or a second connector (C-137). The loss budget calculator turns your board’s share into inches.

What are PCIe transmitter presets?

Eleven standard settings, P0 to P10, of the transmitter’s three-tap equaliser, each a combination of preshoot and de-emphasis (C-18, C-136). P4 is flat; P0 to P3 add only de-emphasis, P5, P6 and P9 only preshoot, P7 and P8 both, and P10 sets its de-emphasis from the low-frequency (LF) level the transmitter advertises during training. The preset table lists all eleven with their tap weights.

How does PCIe link equalization work?

In four phases each time the link moves to a new rate (C-139, C-140). The host hands the card a starting preset for the card’s transmitter (Phase 0); both ends reach the new rate and trade their equalisation abilities (Phase 1); the card tunes the host’s transmitter (Phase 2); and the host tunes the card’s (Phase 3). Each end tunes its own receiver as it goes. The phase diagram walks through it.

Are PCIe 4.0 and 5.0 backward compatible?

Yes. A PCIe 5.0 or 4.0 device works in an older slot, or with an older device, at the highest rate both support; a public PCI-SIG overview gives the example of an x16 PCIe 5.0 device working with an x1 PCIe 1.0 device (C-125). The PCIe 4.0 connector stayed compatible with Gen 1 to 3 (C-137).

What impedance does PCIe use?

The specification allows 70 to 100 Ω differential for the high-speed lanes. Add-in cards are built to 85 Ω so that they work with any host, and the 100 MHz reference clock is routed at 100 Ω (C-142). Vias, capacitor pads and connectors are exempt, but each mismatch is a reflection the receiver has to absorb.

Why PCIe is serial, with an embedded clock

A parallel bus sends a clock alongside the data. A serial link does not — the receiver recovers timing from the data's own transitions, using a clock-and-data-recovery loop.

That removes the hardest problem a wide bus has: skew between a clock and many data wires. With one pair, there is nothing to skew against. It is why serial links scale to rates a parallel bus cannot reach on the same copper.

The cost is that everything now has to survive on one pair. There is no strobe to cancel common-mode delay, the data must contain enough transitions for the loop to track — which is what the encoding is for — and the receiver has to do real work to recover a signal the channel has badly degraded.

What PCIe 4.0 and 5.0 are

A differential serial link, NRZ, at 16 GT/s for Gen 4 and 32 GT/s for Gen 5, with 128b/130b encoding and an embedded clock. The unit interval is 62.5 ps at Gen 4 and 31.25 ps at Gen 5, and the Nyquist frequencies that matter are 8 GHz and 16 GHz. Each doubling of rate doubles the frequency at which the channel has to behave, and loss in dB grows faster than the square root of frequency, so each step has asked more of the channel than the one before.

PCIe 3.0 vs 4.0 vs 5.0, side by side

PCIe 5.0 loss budget: where the decibels go

A realistic system channel is a package, a board escape, several inches of trace, at least one connector, an add-in card, and another package. Every one of those contributes loss and at least one discontinuity. The commonly quoted end-to-end budgets are roughly 28 dB at Gen 4's 8 GHz and 36 dB at Gen 5's 16 GHz, with the split between system board, connector and add-in card set by the CEM (Card Electromechanical) specification rather than by the base spec — the base spec defines the electrical layer, CEM defines the form factor's share of it.

From Gen 3 to Gen 5 the total grew about 1.5 times, while two doublings of the Nyquist frequency multiply a trace’s loss per inch by 2 to 4 times, so on the same laminate the reach shrank. Treat these as sizing figures, not as quotations. Each belongs to a particular specification edition and a particular reference plane, and they are often quoted without those conditions. Before one goes into a budget you are going to defend, take it from the base or CEM document for the revision you are building to — and note that a single number at Nyquist is a screening check, not a description of what the whole waveform experiences.

Thirty-six decibels at 16 GHz means the 16 GHz content of the signal arrives at roughly one part in sixty of what was launched. The low-frequency content is barely attenuated, so what reaches the pad is not a small copy of the launch but a smeared one, and the eye there is typically closed by dispersion. That is expected: the receiver is built to reconstruct the waveform rather than to find it intact.

PCIe Tx presets P0 to P10 and their coefficients

The transmitter’s equaliser has three taps: one for the bit about to be sent (the pre-cursor, c₋₁), the bit being sent (c₀) and the bit just sent (the post-cursor, c₊₁) (C-138). De-emphasis lowers the steady level after a transition and handles the channel’s post-cursor smearing; preshoot raises the bit before a transition and handles the pre-cursor, which the receiver’s DFE cannot, because only the transmitter knows the next bit. The eleven presets fix their mix (C-136):

The tap weights follow from the two dB values once the three taps are scaled to the full swing, |c₋₁| + c₀ + |c₊₁| = 1, and c₀ is what is left. Each preset is nominal: the measured values may sit within ±1 to ±1.5 dB of it (C-136). Tektronix gives the table for 8 and 16 GT/s; PCIe 5.0 also defines P0 to P10 (C-18), so check its values and tolerances against the revision you sign off to. The host chooses the starting preset and the handshake below refines it, by preset or by finer coefficient steps, for the channel actually present (C-139). That is why no single preset suits every board, although by the table’s arithmetic P7 carries the most boost of the fixed presets. The equalisation page shows what each block does to a pulse.

PCIe link equalization: how the link recovers the eye

Equalisation is split across both ends and negotiated at link-up rather than fixed:

• Transmitter presets. Eleven defined combinations of de-emphasis and preshoot (P0–P10), pre-distorting the launched signal to compensate for the channel's slope.
• Receiver CTLE — a continuous-time linear equaliser that boosts high frequencies to flatten the channel, and which amplifies noise and crosstalk along with the signal. The Gen 5 reference receiver offers 11 settings of it (C-138).
• Receiver DFE — cancels the first few post-cursors, two at Gen 4 and three at Gen 5, by subtracting what bits already decided left behind, within a limit on each tap (C-138). It cannot touch pre-cursor, and it propagates its own errors.
• Link equalization. The two ends run a defined negotiation at link-up, requesting transmitter changes, presets or finer coefficient steps, and checking the result, converging on a combination that works for the channel actually present. The channel is characterised at run time, not at design time.

The panel below runs a compressed version of Phases 2 and 3 on a channel you build. The package, connector and add-in card are TI’s allocation for the generation you pick (C-134); the motherboard trace is yours, its laminate given in dB per inch at 16 GHz so the same board is the same board at either rate. The transmitter takes a preset from the table above, launched at 800 mV peak to peak, the low end of a full-swing transmitter as one FPGA vendor quotes it, not a figure tied to either generation (C-198). The receiver tries each of its reference CTLE settings (C-197) and a DFE whose taps stop at their limits (C-138). The eye is judged against TI’s tabulated minimum, 15 mV by 0.3 UI (C-135). Try predicting first: on TI’s Gen 5 channel, does the unshaped preset P4 meet 15 mV, and which preset would you send instead?

How PCIe 4.0 and 5.0 channels are signed off

Compliance judges the eye after equalisation, extrapolated to a target bit error ratio of 10⁻¹² rather than counted bit by bit, which no simulation or bench run could reach in reasonable time. TI tabulates the minimum: an extrapolated eye height of 15 mV and a width of 0.3 UI (one unit interval being one bit time) at Gen 4 and Gen 5, measured after equalisation but, in TI’s case, before the DFE at a redriver output (C-135). The Base specification’s exact reference receiver and procedure are not covered here.

Two habits matter here. Check the S-parameter file for passivity and causality before trusting any of it — a non-causal file produces eye openings that do not exist. And when the budget will not close, the practical options are a lower-loss laminate, a shorter channel, or a retimer; adding equaliser strength beyond the reference model makes the simulation pass without making the link any more likely to.

Why this decides how your board behaves

• Loss is the headline constraint, and it sets reach. The budget is a subtraction and what is left is inches of trace. See channel budgeting.
• Return loss matters more than its decibels suggest. An echo arriving near a sampling instant costs far more than the same energy arriving between samples.
• A resonance is fatal in a way loss is not. The reference equaliser can undo smooth attenuation and cannot restore a cancelled frequency, which is why via stubs and backdrilling get the attention they do on thick boards.
• The eye at the receiver pin may be closed. The useful measurements are then the receiver’s adapted settings and its margin, not an eye photograph at the pin.

What to do about it

Budget by row and name the owner of each. Package, breakout, board, connector, add-in card, far package. The breakout is the row people forget.

Attack discontinuities before attacking loss. Loss is equalisable and predictable; reflections and resonances are neither. Vias, launches and connector footprints first.

Design the stackup for the stub, not just the impedance. Board thickness decides whether a stub resonance lands in band, and exit-layer choice is free where backdrilling is not.

Report adapted equaliser settings, not eye photographs. What the receiver converged to, and how much range it had left, is the margin information. From Gen 4, lane margining measures eye height and width margin at the end of the channel (C-137).

In the real world

PCIe is the interface where the whole toolchain gets exercised: S-parameters, channel simulation, AMI models, compliance masks and a receiver that adapts. It is also where the gap between a channel that meets its budget and a link that works is smallest, because the specification's assumptions are unusually explicit.

The part that still surprises people is how much of the margin lives in structures rather than in trace length — the breakout, the vias, the connector launch. Inches are easy to count and discontinuities are easy to overlook, and the budget is usually lost to the second. PCIe 6.0 keeps the same 16 GHz Nyquist frequency with a tighter 32 dB budget; the PCIe 6.0 vs 5.0 page picks up the story there.

Where the numbers come from

Rates and dates from a public overview by a PCI-SIG board director. Budgets, eye limits and the loss breakdown from a Texas Instruments layout note; presets and the Gen 4 changes from a Tektronix guide; reference receivers from MathWorks’ specification-based models; the equalisation procedure from Teledyne LeCroy and Synopsys. The PCI-SIG Base and CEM specifications are available to members only and have not been read for this page, so every electrical figure is marked scoped in the claim ledger; check limits against the revision you sign off to. Unit intervals, Nyquist frequencies, bandwidths and preset tap weights are arithmetic, checked by the site’s number gate.

Related

• PCIe 6.0 vs PCIe 5.0: PAM4, FLIT, FEC and Signal Integrity
• SerDes Equalization: CTLE, FFE, DFE and CDR
• High-Speed Vias: Stubs, Resonance, and Backdrilling
• Channel Loss Budgeting Across Die, Package, and Board
• Statistical vs Bit-by-Bit Channel Simulation