PCIe 6.0 vs PCIe 5.0: PAM4, FLIT, FEC and Signal Integrity

By Geetansh Arora — Principal SI/PI Engineer1 Nov 202611 min

PCIe 6.0 doubles PCIe 5.0’s 32 GT/s (gigatransfers per second) to 64 GT/s per lane without raising the symbol rate. It switches from NRZ, two voltage levels and one bit per symbol, to PAM4, four levels and two bits, so both generations run at 32 GBd (billion symbols per second) and the channel still has to carry a 16 GHz Nyquist frequency, half the symbol rate. The price is an eye a third as tall, about 9.5 dB less eye height, and a raw error rate high enough that forward error correction, carried in fixed 256-byte flits, becomes part of every 64 GT/s link. An x16 link moves 128 GB/s in each direction before coding.

At a glance

What is PCIe 6.0?

The sixth generation of PCI Express, released by PCI-SIG on 11 January 2022 (C-126). It runs 64 GT/s per lane, twice PCIe 5.0, using PAM4 signalling, a lightweight forward error correction (FEC) with a cyclic redundancy check (CRC) to detect what it misses, and a fixed-size flow-control unit, the flit, to carry them (C-126, C-8a). It is backwards compatible with every earlier generation (C-126).

How fast is PCIe 6.0?

64 GT/s per lane, so an x16 link carries 64 × 16 ÷ 8 = 128 GB/s in each direction: the 256 GB/s that PCI-SIG quotes counts both directions together (C-126). After the flit’s CRC and FEC, 242 of every 256 bytes carry packets and 6 bytes of data-link information: about 121 GB/s each way on x16, 60.5 on x8, 30.3 on x4 and 7.56 GB/s per lane (C-8d). The bandwidth table below gives every generation and link width.

PCIe 6.0 vs PCIe 5.0: what changed?

The data rate doubled and the symbol rate did not: both run at 32 GBd with a 16 GHz Nyquist frequency, NRZ at Gen 5 and PAM4 at Gen 6 (C-125). The channel loss budget at 16 GHz tightened from 36 to 32 dB, the reference receiver grew from a 3-tap to a 16-tap decision feedback equaliser (DFE), and error handling moved from CRC and replay alone to FEC, CRC and replay in 256-byte flits (C-128, C-129, C-132). The side-by-side table lists the rest.

Is PCIe 6.0 backward compatible?

Yes. A PCIe 6.0 device works with PCIe 1.0 to 5.0 devices, and the link runs at a rate both ends support (C-126, C-131). One detail matters on the bench: flit mode is negotiated when the link trains, a 64 GT/s link always runs in it, and once a link has entered flit mode it stays there at every rate, 2.5 GT/s included (C-8a, C-10, C-132).

What is the PCIe 6.0 channel loss budget?

A nominal 32 dB at 16 GHz from root complex (the host end, usually the CPU) to endpoint, 4 dB less than PCIe 5.0’s 36 dB at the same frequency (C-128, C-6b). In an add-in-card system about 23.5 dB of it belongs to the system side and 8.5 dB to the card, which leaves the motherboard about 15.7 dB for its traces, vias and capacitors (C-130). Exactly where the budget is measured, and how retimers (chips that recover and resend the signal part-way along) change it, are set in the Base specification, which this page has not read.

What about PCIe 7.0?

PCI-SIG released PCIe 7.0 to its members on 11 June 2025: 128 GT/s, still PAM4 and flits, and up to 512 GB/s for an x16 link counting both directions (C-127). PAM4 is already in use, so this doubling has to come from the symbol rate, which works out to 64 GBd and a 32 GHz Nyquist frequency, twice what the Gen 6 channel carries. Pathfinding for PCIe 8.0 was already under way at that release (C-127). The 7.0 channel budget is not covered here.

What is a flit in PCIe 6.0?

A flow-control unit: a fixed 256-byte block that carries 236 bytes of transaction-layer packets, 6 of data-link information, 8 of CRC and 6 of FEC (C-8d). A block code needs the same bytes every time to compute its check bytes over, which variable-length packets cannot give it. At 64 GT/s on x16 one flit passes in 2 ns. The flit diagram draws it to scale.

How much latency does PCIe 6.0 FEC add?

Very little, by design. PCIe 6.0 was specified to add under 10 ns to transmitter plus receiver over a 32 GT/s link, FEC included, and the FEC correction and CRC check together take under 2 ns (C-131, C-132). That is why the code is light: it corrects short bursts quickly and leaves anything worse to the CRC and a replay. A new power state, L0p, lets a link scale its power with the bandwidth in use without stopping traffic (C-131).

PCIe 5.0 vs PCIe 6.0 · one symbol, the same swing

Twice the data, the same frequency. PCIe 6.0 sends two bits in each 31.25 ps symbol where PCIe 5.0 sent one, so both run at 32 GBd and the channel still carries a 16 GHz Nyquist frequency. The four levels share the swing that held two, so each of the three eyes is a third as tall: 20·log₁₀(3) ≈ 9.5 dB less. The eyes are a little narrower too, because a step between adjacent levels slews more slowly than a full-swing one (C-133). A cartoon, not a simulated eye; Gen 6 accepts a raw error rate no worse than about 10⁻⁶ and lets FEC and replay clean it up (C-131).

Why the rate could not simply double again

PCIe 1.0 to 5.0 each raised the symbol rate: 2.5, 5, 8, 16 and 32 GBd. Gen 5 runs at 32 GT/s NRZ, so doubling it the same way would mean 64 GBd and a 32 GHz Nyquist frequency.

Loss in a board trace, in dB, grows between the square root of frequency and in step with it, and faster still where the laminate’s loss tangent rises, so a channel that loses 36 dB at 16 GHz would lose roughly 51 to 72 dB at 32 GHz. The 112G vs 224G Ethernet page works through why the factor lands between √2 and 2. A channel that long would leave the receiver no eye to recover.

So Gen 6 changes the modulation instead. Four voltage levels, two bits per symbol, the same 32 GBd symbol rate, and therefore the same Nyquist frequency as Gen 5. The channel’s job stays familiar. The receiver’s gets harder. The NRZ vs PAM4 panel runs exactly this trade at 64 GT/s: change the channel’s loss and watch which eye stays open.

The trade PAM4 makes

Keeping Nyquist where it was moves the cost into amplitude. Three eyes have to fit in the swing that previously held one, so each eye is a third the height:

SNR penalty = 20·log₁₀(3) ≈ 9.5 dB Eye height at the same swing and the same noise. The slower steps between adjacent levels cost some eye width as well (C-133).

There is a second, subtler cost: the three eyes are not identical. Level-dependent nonlinearity in the driver makes the outer eyes and the inner eye behave differently, so transmitter linearity becomes something to measure in a way it never was for NRZ, and test-equipment vendors describe new PCIe 6.0 transmitter measurements for it (C-34).

PCIe 6.0 vs 5.0, side by side

What changed for signal integrity (ledger rows in brackets; electrical values as reported from the Base specification)
	PCIe 5.0	PCIe 6.0
Released	2019 (C-125)	11 Jan 2022 (C-126)
Data rate per lane	32 GT/s	64 GT/s (C-125)
Signalling	NRZ, 1 bit per symbol	PAM4, 2 bits per symbol (C-125)
Symbol rate; one symbol	32 GBd; 31.25 ps	32 GBd; 31.25 ps
Nyquist frequency	16 GHz	16 GHz
Eye height, same swing	one eye, the full swing	three eyes, a third each: −9.5 dB
Channel loss at 16 GHz	36 dB (C-6b)	32 dB (C-128)
Reference CTLE	4 poles, 2 zeros	6 poles, 3 zeros (C-129)
Reference DFE	3 taps	16 taps (C-129)
Line code	128b/130b (C-125)	256-byte flit (C-8d)
Error handling	CRC and replay (C-132)	FEC, CRC and replay (C-126)
Raw error target	—	first bit error rate no worse than about 1e-6 (C-131)
Transmitter linearity	—	ratio of level mismatch (RLM) and signal-to-noise-and-distortion ratio (SNDR), new in 6.0 (C-34)
New power state	—	L0p, power scales with bandwidth used (C-131)

Why Gen 6 adds FEC

PAM4 costs 9.5 dB of eye height, far more than the 4 dB the tighter channel budget gives back. Gen 6 closes the gap in three ways: a stronger reference receiver with a 16-tap DFE, a channel budget cut from 36 to 32 dB, and a relaxed raw error target (C-128, C-129). That target is a first bit error rate no worse than about 10⁻⁶: it counts the first error of each burst, before DFE error propagation adds more (C-131). Forward error correction, the CRC and replay then deliver the reliability. PCI-SIG’s stated target is a failure-in-time rate well below one failure per billion hours for an x16 link, and vendors quote a delivered error rate near 10⁻¹² (C-131, C-9). The link is designed knowing the correction is there.

That requires a fixed-size transport to carry the code words, which is what flit mode provides: fixed-length flow control units with FEC and CRC in known positions. Flit mode is negotiated when the link trains; a 64 GT/s link always runs in it, and a link in flit mode stays there at lower rates too (C-8a, C-10, C-132).

Inside a PCIe 6.0 flit · 256 bytes, drawn to scale

Fourteen bytes in every 256 buy the error correction. A public overview by a PCI-SIG board director divides the flit into 236 bytes of transaction-layer packets (TLPs), 6 of data-link-layer information, drawn as “link”, 8 of CRC and 6 of FEC (C-8d). The FEC is three interleaved codes that each correct one byte, so any burst up to 3 bytes long is fixed in place; the CRC is guaranteed to catch up to 8 bad bytes, and a flit that fails it is sent again (C-132).

Four mechanisms, four jobs (C-8a to C-8c, C-132)
Mechanism	Its job	Its limit
Flit	a fixed 256-byte block, so the code always protects the same bytes	14 of every 256 bytes go to CRC and FEC
FEC	corrects the common case on the fly: any burst up to 3 bytes	a longer burst, or more errors than one per interleave
CRC	detects what the FEC missed, guaranteed up to 8 bad bytes	corrects nothing
Replay	resends the failed flit from the sender’s buffer: that flit alone when it can, or everything from it onward	costs bandwidth and latency each time

Precoding completes the picture. A DFE that makes a wrong decision feeds that error back and can produce a burst, and burst errors are exactly what a lightweight FEC handles worst. Precoding at the transmitter limits how many errors one wrong DFE decision can cause, so a burst leaves fewer bad symbols for the FEC (C-131); the deeper section below shows how.

The change that most affects day-to-day work A first bit error rate of 10⁻⁶ is measurable. At 64 GT/s a new error burst starts about every 16 microseconds on one lane — a bathtub curve you can actually acquire rather than extrapolate. That removes one large source of uncertainty in sign-off: fitting Gaussian tails six decades below anything observed. It does not remove all of it. Whether FEC delivers depends on how the errors cluster, and a raw error rate says nothing about that; the burst point below is the other half of the picture.

How light can the code be? Take errors that arrive one at a time at a first-bit error rate (FBER) of 10⁻⁶. A byte goes bad about once in 125,000, so a flit only needs replaying when two bad bytes land in the same one of the three codes: about 7 flits in ten million, one replay every 2.9 ms on an x16 link whose flits last 2 ns. Before you try the panel, predict what happens to that number if each error has an even chance of spoiling the next byte too.

Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.

Raw errors in, replays out numerical flits hit — FEC fixes — replayed — a replay every — this flit —

One flit, 256 bytes in lane order · tinted by FEC code

code 0code 1code 2bad, correctedbad, replayed

The chance a flit is replayed · against the raw error rate

any bad bytereplayed, errors alonereplayed, in bursts

FBER1.0×10⁻⁶

Bursts0%

Link width

On the map

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Where the 32 dB goes

Gen 6 kept Gen 5’s Nyquist frequency but not its budget: the channel may lose a nominal 32 dB at 16 GHz end to end, against 36 dB before (C-128, C-6b). Split the way Synopsys and Tektronix describe it for an add-in card, about 23.5 dB sits on the system side and 8.5 dB on the card, whose share includes a 4.6 dB package. The motherboard is left about 15.7 dB for its traces, vias and AC-coupling capacitors from the root port to the slot, and the same paper expects motherboards to carry retimers and better laminate as a result (C-130). PCI-SIG’s goal was a reach similar to PCIe 5.0 in a similar set-up, with at most two retimers (C-131).

The channel budget at 16 GHz · PCIe 5.0 vs PCIe 6.0, drawn to scale in dB

Gen 6 kept the frequency and gave back 4 dB. Both bars are end-to-end channel budgets at 16 GHz on one scale: 36 dB for PCIe 5.0 and 32 dB for PCIe 6.0 (C-6b, C-128). The PCIe 6.0 split is the add-in-card example Synopsys and Tektronix describe: about 23.5 dB for the system side, of which about 15.7 dB is left for motherboard traces, vias and capacitors, and 8.5 dB for the card, including a 4.6 dB package (C-130). The bracket shows the size of the board’s share, not where it sits along the path.

Take the vias, capacitors and breakouts out of the 15.7 dB first; the loss budget calculator turns what is left into inches of trace for your laminate, and channel budgeting covers how the pieces add up.

What stays the same

Because Nyquist has not moved, the channel work is familiar: loss is judged at the same 16 GHz, via stubs resonate at the same frequencies, and the connector and breakout discontinuities are the same ones. What changes is how little margin there is to absorb any of it: 4 dB less loss allowed, and every reflection or crosstalk aggressor landing on an eye a third the size.

Why this decides how your board behaves

Everything that is not loss now matters three times more. Crosstalk, reflections and supply noise all eat three times the fraction of an eye they did at NRZ.
Return loss matters more. A reflection now lands on an eye a third the height, so backdrilling, launch design and connector footprints matter as much as the laminate, which the same Synopsys and Tektronix paper expects to improve on Gen 6 boards too (C-130).
A high raw error rate is normal. Designing to an NRZ instinct about acceptable raw BER leads to over-design; reading a raw number as a failure leads to alarm.
Burst structure matters now. FEC has a limited burst-correcting capacity, so errors that arrive together are worse than the same number arriving independently.

What to do about it

Re-budget noise, not just loss. The temptation is to reuse a Gen 5 channel because Nyquist did not move. The loss budget tightens by 4 dB, but the eye is 9.5 dB smaller and the stronger equaliser wins back only part of that, so budget crosstalk, reflections and supply noise explicitly instead of carrying over Gen 5’s margins.

Check all three eyes. They are not identical — transmitter level linearity and threshold placement affect them differently — and reporting one number for a PAM4 link is incomplete.

Separate raw and post-correction error rates in every report. Quoting one as the other is the most common confusion on this topic.

Look for sources of bursty errors specifically. DFE error propagation and periodic aggressors produce exactly the structure FEC handles worst.

Using this to find a fault

One eye much worse than the other two. Level linearity or threshold placement — usually a device issue, since the channel treats all three alike.
Post-FEC errors with an acceptable raw rate. Bursts. Look at error spacing, not just error count.
A channel that was comfortable at Gen 5 and marginal at Gen 6. Measure loss against the new 32 dB, then check crosstalk and return loss: the frequency did not change, but the budget shrank by 4 dB and every eye by two thirds.

PCIe 1.0 to 7.0: GT/s and GB/s by lane count

Every generation has roughly doubled the bandwidth per lane (C-125, C-127), but not always by doubling the transfer rate. Gen 3 raised the rate only 1.6 times, from 5 to 8 GT/s, and made up the rest by changing the line code from 8b/10b, which spends 20% of the bits on coding, to 128b/130b, which spends 1.5%. Gen 6 doubled with PAM4 instead of a faster symbol rate, and Gen 7 doubles the symbol rate again.

PCIe generations (C-125, C-126, C-127); symbol rate and Nyquist frequency follow from the signalling
Generation	Released	Transfer rate	Signalling, line code	Symbol rate	Nyquist
PCIe 1.0	2003	2.5 GT/s	NRZ, 8b/10b	2.5 GBd	1.25 GHz
PCIe 2.0	2007	5 GT/s	NRZ, 8b/10b	5 GBd	2.5 GHz
PCIe 3.0	2010	8 GT/s	NRZ, 128b/130b	8 GBd	4 GHz
PCIe 4.0	2017	16 GT/s	NRZ, 128b/130b	16 GBd	8 GHz
PCIe 5.0	2019	32 GT/s	NRZ, 128b/130b	32 GBd	16 GHz
PCIe 6.0	2022	64 GT/s	PAM4, flit	32 GBd	16 GHz
PCIe 7.0	2025	128 GT/s	PAM4, flit	64 GBd	32 GHz

PCIe bandwidth by link width, GB/s in each direction: after 8b/10b or 128b/130b line coding for 1.0 to 5.0, after the flit’s CRC and FEC for 6.0, and the raw rate for 7.0 (*)
Generation	x1	x4	x8	x16
PCIe 1.0	0.25	1.0	2.0	4.0
PCIe 2.0	0.5	2.0	4.0	8.0
PCIe 3.0	0.985	3.94	7.88	15.8
PCIe 4.0	1.97	7.88	15.8	31.5
PCIe 5.0	3.94	15.8	31.5	63.0
PCIe 6.0	7.56	30.3	60.5	121
PCIe 7.0	16*	64*	128*	256*

Line coding takes its share first: 8b/10b keeps 80% of the bits, 128b/130b keeps 98.5%, and a Gen 6 flit keeps 242 of its 256 bytes, 6 of which are data-link information; packet headers and flow control come out of what is left in every generation. That is not quite like for like: the flit also drops the sync headers, framing tokens and per-packet CRCs that Gen 5 pays for on top of 128b/130b, and PCI-SIG aimed for under 2% bandwidth inefficiency against Gen 5 (C-131). *The Gen 7 row is the raw rate, transfer rate × lanes ÷ 8, because the sources used here do not give its flit layout. So a Gen 4 x4 SSD link carries 7.88 GB/s each way, Gen 5 x4 15.8 GB/s, and a Gen 5 x16 graphics slot 63.0 GB/s. PCI-SIG’s headline figures are raw and count both directions: 256 GB/s for a Gen 6 x16 link and 512 GB/s for Gen 7 (C-126, C-127).

Go deeper — the mechanisms Gen 6 adds, and what they are each for

Precoding: breaking DFE error bursts. A decision feedback equaliser subtracts what the previous symbols left behind, using its own decisions. When one decision is wrong, the wrong correction is subtracted from the next symbols too, and a single noise event can become a run of errors. A run is what a lightweight FEC handles worst: its correction capacity is bounded per code word, and a burst can exceed it where the same number of scattered errors would not.

In its usual form, 1/(1+D), precoding at the transmitter encodes each symbol relative to the one before it, and the receiver undoes that by combining each decision with the previous one. A DFE error run alternates in sign, so after decoding it leaves an error at its start and one at its end rather than one per symbol. The burst becomes two isolated errors, which is the shape the FEC was sized for. The precoder’s exact definition, and when a link enables it, are in the Base specification.

The fixed-size FLIT, and why the FEC is light. Earlier generations sent variable-length packets. A block code needs fixed blocks to compute parity over, so Gen 6 carries everything in fixed 256-byte flow control units, with the FEC and a CRC in known positions (C-8a to C-8c). A public overview by a director of the PCI-SIG board divides the 256 bytes into 236 of transaction-layer data, 6 of data-link information, 8 of CRC and 6 of FEC (C-8d; the overview was read, the specification itself was not).

The code is deliberately light, because a load-store interconnect cannot wait for a long decode. Gen 6 was designed to add under 10 ns to transmitter plus receiver over a 32 GT/s link, FEC included, and the same overview contrasts that with the roughly 100 ns FEC latency of PAM4 networking (C-131); the long Ethernet RS(544,514) code belongs to that family. Correction and the CRC check take under 2 ns (C-132). A flit lasts 256 × 8 bits ÷ (64 GT/s × 16 lanes) = 2 ns on x16 and 32 ns on x1. What the FEC cannot correct, the CRC detects, and the link replays that flit from the partner’s buffer: the flit fixes the block, the FEC corrects the common case, the CRC catches the rest, and replay recovers it.

Transmitter linearity. An NRZ transmitter is judged on swing and edges. A PAM4 transmitter also has to place its four levels evenly: a driver that compresses near its rails squeezes the outer eyes, and noise that would be harmless on an even eye then lands on a short one. Gen 6 therefore specifies linearity, as a ratio of level mismatch, RLM (how unevenly the four levels are spaced), and as a signal-to-noise-and-distortion ratio, each measured through a defined test setup (C-34). Take the limits from the revision you sign off to; they are not reproduced here because the specification has not been read for this page.

A stronger reference receiver. Compliance scores a channel through a reference receiver, and Gen 6’s is stronger: a CTLE with six poles and three zeros against four and two, and a 16-tap DFE against 3 taps (C-129). More DFE taps cancel more of the reflections that arrive a few symbols late, which is part of how a 32 dB channel with a third of the eye still closes. The equalisation page explains each block.

In the real world

Gen 6 changes the character of signal integrity work on PCIe more than any previous generation did. NRZ debugging was mostly about loss and reflections, which are fixed with geometry and materials. PAM4 debugging is mostly about noise, linearity and error statistics.

The practical consequence is that the first instinct has to change. On a marginal NRZ link the question was usually “how do I get less loss?”. On a marginal Gen 6 link it is more often “what is adding noise, and does it arrive in bursts?”. PCIe 7.0 adds the old question back: at 128 GT/s the Nyquist frequency doubles to 32 GHz, so for a similar channel loss returns to the top of the list as well.

Where the numbers come from

Rates, dates and headline bandwidths from PCI-SIG’s own press releases and a public overview by a PCI-SIG board director. The channel budget, its split and the reference receiver from test-equipment, IP and connector vendors who quote the specification. The PCI-SIG Base specification is available to members only and has not been read for this page, so every electrical figure is marked scoped in the claim ledger; check limits against the revision you sign off to. Bandwidths, symbol rates and Nyquist frequencies are arithmetic on those rates, checked by the site’s number gate.

Sources

Rows marked with a claim id are tracked in the claim ledger, which records what each source can and cannot establish.