Power Integrity / 07
DC IR Drop and Electromigration
Before any of the interesting dynamic behaviour happens, plain DC resistance has already taken a slice of your voltage budget — and it takes it permanently. The same current density that causes it also, over years, physically moves metal atoms and opens the conductor. Two failures, one cause, very different timescales.
Ohm's law, before anything else happens
Before high-speed clock trees ever start switching and before nanosecond transients, package anti-resonances, or cavity modes can develop, the most fundamental law of electronics is already taking its cut: Ohm's law (V = I × R). Copper is a superb conductor, but it is not a superconductor. Every milliohm of resistance across board copper planes, via barrels, solder balls, and dense on-die power grids drops voltage whenever DC current flows.
When modern low-voltage processors demand tens or hundreds of amperes of current, that static I × R drop permanently takes a large share of the allowed voltage window before dynamic AC noise even enters the picture. Furthermore, when that immense current is forced through microscopic solder balls or narrow metal necks, extreme current density does something far more permanent: billions of energetic electrons physically collide with metal atoms, knocking them out of position and migrating them downstream. Over months or years, this electromigration carves voids that eventually snap the conductor into a permanent open circuit.
Every conductor between the regulator and the transistor has resistance: plane copper, vias, BGA balls, package traces, and the metal grid on the die itself. Push current through resistance and you drop voltage. That is all IR drop is.
What makes it consequential is that it is static. It is not a transient you can ride out or a resonance you can damp. It is simply gone, before the rail has done anything interesting, and everything dynamic has to fit in what is left.
The budget is spent before the AC arrives
IR drop is the least interesting mechanism in power integrity and one of the most consequential, because it comes off the top. A 5% ripple budget on a 0.75 V rail is 37.5 mV total. If DC drop from the regulator sense point to the transistor takes 20 mV of that, everything dynamic — droops, resonances, SSN — is fighting over the remaining 17.5 mV.
The resistance is distributed across the whole chain, and the share is rarely where people expect: board planes contribute least per unit length because they are wide, while vias, BGA balls, package traces and the on-die power grid contribute most. On a high-current rail the on-die grid is frequently the single largest term, which makes it a floorplanning problem before it is a board problem.
Watch the plane turn to Swiss cheese
Here is that map, solved as you change it. The panel below is a power plane in 1 oz copper, fed along its left edge by the regulator, under one corner of a BGA at 1 mm pitch. In the middle of the array is the core: power vias, in blue, alternating with ground vias. Around it are two rings of signal and ground vias. Every via that is not a power via passes through the plane in a clearance hole, its antipad, and every amp for the core has to find its way between those holes.
Before you touch anything, predict what happens when the holes grow. The copper left between two neighbouring holes is a neck, as wide as the pitch minus the antipad diameter: at a 0.9 mm antipad on a 1 mm pitch that is 0.1 mm of copper. Slide the antipad diameter and watch three things. The shading is current density as a multiple of the open plane to the left of the array, where 20 A in this sheet is about 49 A/mm². The grey lines are equipotentials, and they bunch wherever the voltage is being lost. The plot below the map traces the drop against hole size, with your budget across it.
The drop does not rise steadily. It barely moves while the necks are wide, then climbs ever faster as they close, because the resistance of a neck grows without limit as its width goes to zero. When the holes are as wide as the pitch they touch, the rings become a wall, and the core is cut off from the regulator altogether. On a real board this is easy to miss, because a layer plot zoomed out to the whole package shows the plane as continuous; the walls only appear at the scale of the necks.
The second plot is the other half of the lesson. Even with no antipads at all, the power vias nearest the regulator carry more than their share, because their path is shorter. As the necks close, that imbalance grows. Then tap a via on the map to change it: a ground or signal via becomes an empty site, an empty site becomes a power via, and a power via becomes ground. Clear a lane through the rings, or press Feed channel, and see what a gap in the right place is worth. Then push the antipads to 1 mm and watch the lane keep the core connected after the rest of the ring has closed. This is the “fix crowding with geometry” advice below, made concrete.
Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.
Electromigration: the same current, a different failure
Push enough current density through a metal conductor and momentum transfer from the electrons physically displaces metal atoms. Material migrates downstream, voids open upstream, and eventually the conductor fails open. The rate is captured by Black's equation:
Two consequences follow. First, EM is a lifetime specification, not a pass/fail measurement — you cannot see it at bring-up, and the part that fails EM works perfectly for months. It is enforced by design rules: a maximum current density per metal layer, per temperature, per bump or ball, checked by rule rather than observed.
Second, the temperature term ties EM to thermal design in a way that catches people out. A layout that passes at the nominal junction temperature can fail at the thermal corner, and a rail that is fine in isolation can be marginal once a neighbouring block heats it. Signing off EM at typical temperature is not a conservative simplification; it is the wrong corner.
Why this decides how your board behaves
- It comes off the top of the budget. Whatever DC drop takes, the AC analysis never sees. A design that allocated its full ripple budget to dynamic impedance and then discovered 20 mV of DC drop has lost half of it after the fact.
- The worst point is not the average. Current crowds — at plane cutouts, around via arrays, into whichever balls sit on the lowest-resistance path. A rail can meet its average current density everywhere and still have individual balls carrying several times their share.
- It is usually a die and package problem, not a board one. Board planes are wide and contribute least per unit length. The on-die power grid is frequently the single largest term, which makes it a floorplanning question before it is a layout one.
- It interacts with timing. A gate at the far end of a grid runs at a lower supply than one near the pins, so it is slower. Static IR drop becomes a systematic timing skew across the die.
What to do about it
Allocate the DC drop explicitly, at the start. Decide what fraction of the tolerance belongs to static drop before the dynamic analysis begins, and hold that line. This is a budgeting decision, not a measurement.
Check the map, not the average. A current-density plot with a colour scale hides exactly the hot spots that matter. Look at the maximum, and look at where it is.
Put the sense point where the specification means. A regulator regulates what it senses. Sensing at its own output regulates the output and lets all the drop fall on the load; sensing at the load moves the drop inside the loop where the regulator corrects it, at the cost of loop stability margin. Remote sense is the single highest-leverage decision here.
Fix crowding with geometry, not with more copper overall. Widening a plane that is already wide does little; adding vias where the current is being forced through a narrow path does a great deal.
- Voltage measured at the load lower than at the regulator. That difference is your IR drop, directly. Measure it under load, not at idle — it scales with current.
- A rail that fails only at high load and recovers instantly. Static drop, not a transient. A transient would show a settling shape; drop simply tracks the current.
- Timing failures that correlate with physical position on the die. Grid drop. The far end of the grid is running slower because it is running lower.
- A device that fails after months in the field with no visible damage. Consider electromigration on a via or ball array, especially one that a current-density check passed on average.
Go deeper — Black's equation and what it does not license
Electromigration is the long-term failure driven by the same current density. Electrons transfer momentum to metal ions; over time, material migrates downstream, voids open upstream, and the conductor eventually fails open. Black's equation captures the rate:
Two things about that expression are worth stating carefully, because it is routinely over-applied.
The exponential in temperature is the dominant term. A modest temperature rise shortens life far more than a modest current increase does. Which means an electromigration assessment without a thermal analysis behind it is not an assessment — the T in that exponent is the junction or conductor temperature under real operating conditions, not ambient.
n and Ea belong to a specific metallurgy. They are fitted constants for a particular metal, barrier, grain structure and geometry, measured by accelerated test. They are not universal, and a lifetime number computed with borrowed constants is not a prediction. The honest use of Black's equation is comparative — this via array is worse than that one — rather than absolute.
This is also why the reliability rules you are given are stated as current-density limits rather than as lifetimes. The limit already encodes somebody's metallurgy, temperature assumption and target life. Applying it is sound; back-calculating a lifetime from it is not.
Why DC matters and AC mostly does not. Electromigration is driven by net atomic transport, so a current that reverses direction largely undoes its own damage — there is a partial self-healing effect. A rail carrying steady DC is the classic case; a signal line carrying balanced AC is largely exempt at the same RMS density. That asymmetry is why power delivery gets the reliability scrutiny and signal routing usually does not.
How the panel above works
The plane. At DC a copper plane is a sheet of resistance, and its thickness sets the resistance of one square of it, of any size: Rs = ρ/t. For 1 oz copper, 35 µm thick, that is 0.49 mΩ per square. The solver cuts the plane into cells 0.2 mm across and joins each to its neighbours with a conductance set by how much copper the face between them actually has. That length is computed exactly against the circle of every antipad, so a neck narrower than a cell still has its true width. Kirchhoff’s current law at every cell gives a set of linear equations, solved by conjugate gradients.
The vias. Each power via’s pad is one node in the plane. Below it is a plated barrel, 0.25 mm drilled with 25 µm of copper, about 0.97 mΩ per millimetre of length, and a solder ball of roughly 0.33 mΩ. All of them meet at the package, which is treated as one node. That is why the via shares depend on the plane: a via with a shorter, wider path through the copper sees less resistance in series with the same barrel, so it takes more current.
The numbers it reports. The drop is from the regulator’s edge to the worst power via pad, in the plane alone, not through the barrel and ball. The neck density is the current through the narrowest copper between two neighbouring antipads, divided by its width and the copper thickness: a mean across the neck, which converges as the grid is refined, rather than the peak at its edges, which on a fine enough grid would not. The solver has been checked against an exact uniform strip and against the known extra resistance of one small round hole in a strip, and the 0.2 mm grid agrees with a grid four times finer to within a percent or two.
What it leaves out. One plane and one rail; a real board has several planes in parallel and the other rail’s return beside it. The regulator is a perfect edge, the package is a perfect node, and copper resistance does not rise as the necks heat, which at the densities the narrowest necks reach it would. Mechanism and proportion, not a sign-off number.
In the real world
IR drop can quietly consume a meaningful part of a power-integrity budget. It may not cause a dramatic failure by itself; instead, the design can lose margin across many conditions when dynamic analysis begins from a rail budget already partly consumed by DC drop.
The habit worth building is to write the allocation down: so many millivolts to set-point error, so many to static drop, so many to dynamic. It takes five minutes at the start of a project and it makes every later argument about the PDN a conversation about numbers instead of instincts.