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Fundamentals / 05

TDR (Time-Domain Reflectometry): Reading PCB Impedance

By Geetansh Arora — Principal SI/PI Engineer10 min

A time-domain reflectometer sends a fast step into a channel and records what comes back. Every change in impedance returns part of the step, and it returns after the time it takes to get there and back, so the trace is a map: time on the screen is distance along the channel, and the height of the trace is the impedance there. Reading it well is mostly a matter of knowing what the edge hides.

Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.

Build a channel · read its TDR numerical edge length — resolves — round trip to the load — lowest — highest —
What the TDR reads, over the channel as built
what the TDR readsthe channel as built
What the instrument records: reflection against round-trip time
reflection coefficient ρ

What the instrument does

A TDR is a step generator and a sampling scope on the same port. The step travels down the channel, and wherever the impedance changes, part of it is reflected with the coefficient from the reflections page, Γ = (Z2 − Z1)/(Z2 + Z1). The scope sees each reflection arrive back at the port. A reflection from a feature at distance x has travelled to it and back, so it arrives at the round-trip time 2x/v. At 170 ps per inch, typical of stripline, each inch of trace is 340 ps of round trip.

The instrument records the reflection coefficient ρ against that time, and most will also show it as an impedance, by inverting the same formula:

Z(t) = Z0 · (1 + ρ) / (1 − ρ)      x = t · v / 2 exact for the first reflection; everything behind it is seen through what came before

The panel above does exactly that. Its lower chart is the raw record, ρ against round-trip time. Its upper chart converts both axes, to impedance against distance, and draws the channel as it was built underneath, so you can see where the reading tells the truth and where it does not.

Reading the shapes

Most of what a TDR shows is a handful of shapes. Learn them first, and the numbers make sense afterwards.

Six shapes to recognise · each one computed by the panel’s model, not drawn
a dip shunt C: via, pad a bump series L: a neck a step down and back a lower-Z section a slow climb loss, uniform line up to +1 an open end down to −1 a short dashed: no reflection, ρ = 0 · each panel scaled to fit
Read the shape first, then the number. Each panel is the reflection a 35 ps edge gets back from one feature in an otherwise matched 50 Ω line, time running left to right. A shunt capacitance, a via or a pad, pulls the reflection down while the edge charges it: a dip. A series inductance, a narrow neck or a wire, pushes it up: a bump. A run at a lower impedance steps down and comes back at its far end. A lossy line that is perfectly uniform still climbs slowly, because the reading includes more series resistance the further the edge has gone. An open end goes to +1 and a short to −1. Each panel has its own vertical scale, so compare shapes here and sizes in the panel above.

A dip is capacitance: a via barrel, a pad that is wider than the trace, a component land. A bump is inductance: a neck where the trace narrows, a wire bond, a connector pin with no return close to it. A lumped feature reads as a dip or a bump that comes back to the line’s impedance afterwards. A section at another impedance reads as a step that holds for as long as the section lasts. The far end decides the last shape: matched, the trace stays flat; open, it climbs to +1; shorted, it falls to −1.

The edge sets what you can see

The edge is not instantaneous, and that limits everything. A feature’s reflection is smeared across the edge’s duration, so two features whose reflections arrive less than about one rise time apart merge into one. The reflections are separated by twice the distance between the features, which gives the usual rule:

Δx ≈ tr · v / 2 a 35 ps edge resolves about 0.10 in at 170 ps/in; a 10 ps edge about 0.03 in

Choose “Two vias, one dip” in the panel: two identical vias 10 ps apart read as a single, deeper dip, and nothing in the trace says there are two. “The same two, faster edge” shortens the edge to 10 ps and they separate. Resolution is set by the edge, not by how finely the scope samples.

The same smearing means a short feature never shows its true impedance. A 35 Ω neck that is shorter than the edge is over before the reading has finished falling, so it bottoms out well above 35 Ω. Lengthen the section in the panel and watch the reading settle at the true value once the section is longer than the edge. A reading is only an impedance where it is flat.

For a lumped feature there is a better measure than the depth: the area. However fast or slow the edge, the area of a capacitive dip, in ρ times time, is Z0·C/2, and the area of an inductive bump is L/(2·Z0). A faster edge makes the dip deeper and narrower, never bigger. Integrating the dip is how a via’s capacitance is estimated from a TDR.

Why the reading drifts

Loss makes a uniform line climb. On a lossy trace the reading rises slowly with distance, even when the line is perfectly uniform and matched. The line’s series resistance is part of the impedance the edge sees, and the further the edge has travelled, the more of it the reading includes. Choose “Loss makes the line climb” to see it. A rising baseline on a lossy trace is not a taper, and judging a long line’s impedance from its far end overstates it.

Everything behind a mismatch is seen through it. The formula above is exact only for the first reflection. Behind a large discontinuity, the step that reaches the next feature has already lost part of itself, and part of what that feature returns is reflected again on the way back. The levels behind it are wrong, and they can be wrong in either direction. “Masking behind a mismatch” puts a 70 Ω load behind a 30 Ω section; the first level the load shows is not 70 Ω. Undoing this needs layer peeling, which reconstructs the impedance one reflection at a time, or a model of the whole channel.

Go deeper — the areas, TDR from a VNA, differential TDR, and the reference plane

Why the area does not depend on the edge. A shunt capacitance C on a line of impedance Z0 reflects Γ(s) = −s·Z0·C / (2 + s·Z0·C). The reflection of a step is Γ(s)/s, and the area under any response is its value at s = 0: −Z0·C/2. Band-limiting the step filters the response but leaves its integral alone, so the area is the same for every edge. A series inductance L gives +L/(2·Z0) the same way. For the 0.5 pF via in the panel’s first scenario that is 12.5 ps of ρ·time; for a 1 nH bump, 10 ps.

TDR from a vector network analyser. A VNA measures S11 against frequency; an inverse Fourier transform turns it into the same time-domain picture, and this panel computes its trace that way. The VNA’s top frequency sets the effective rise time, and the window applied before the transform trades ringing against sharpness. Two instruments with the same bandwidth and different windows draw the same feature differently, so a VNA-derived TDR should state both.

Differential TDR. A differential pair is measured by driving its two lines with opposite steps, which reads the odd-mode, or differential, impedance; driving them together reads the common mode. Skew between the two steps mixes the modes, and so does any asymmetry in the pair. The single-ended panel above does not show this.

The reference plane. Distance is measured from wherever the instrument was calibrated, usually the end of its cable or probe. A launch, a probe tip or a fixture between that plane and the board adds its own dips and bumps at the start of the trace; de-embedding moves the plane past them.

In the real world

The everyday use is controlled-impedance verification. Fabricators build a test coupon beside the board, a straight trace of the same construction, and read its impedance on a TDR in the flat region away from both ends. Away from the ends matters: the launch at the start and the open at the far end are features, not the trace, and on a lossy coupon the reading climbs along the length.

In bring-up and debug a TDR finds what a schematic cannot: a via that dips more than its neighbours, a connector that bumps, an unused stub that rings, a break that reads as an open. Convert the time to distance, at the propagation velocity of the layer the trace is on, and you know where on the board to look. The same measurement on a cable finds the distance to a fault.

The limits are the ones this page is about. The edge at the board is slower than the instrument’s own, because the cable and probe in between have loss; features closer than that edge merge; short features read shallow; and everything behind a large mismatch is distorted. Read the flat regions as impedances and the rest as shapes.

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