Power Integrity Interview Questions and Answers

Short answer. Making sure every device on a board receives a supply voltage that stays within its tolerance while its current changes, from DC to the fastest current step it draws. It covers the regulator, the planes and capacitors on the board, the package, and the capacitance on the die.

A strong answer adds. It has a DC half, the resistive drop and current density that take a permanent slice of the voltage, and an AC half, the noise when the load current changes faster than the network can respond. Its consequences show up in signal integrity too: supply noise moves logic thresholds and edge timing, which becomes jitter.

Likely follow-up: Why has it become harder? Supply voltages have fallen and currents have risen, so the same percentage tolerance is fewer millivolts across more amps.

Read: Power Delivery Network (PDN) Basics: VRM to Die · DC IR Drop and Electromigration

Short answer. The highest impedance the power network may present to the load without the voltage moving more than allowed: Z_target = V_dd×ripple / ΔI. A 0.8 V rail with 3% allowed ripple and a 20 A step needs 1.2 mΩ.

A strong answer adds. The ripple in that formula is only what is left after DC tolerance, regulator accuracy and IR drop have taken their share, and it should be the same peak or peak-to-peak convention as the budget. The target applies over the frequencies where the load current has energy; a flat line from DC to infinity is a simplification, because the board cannot control impedance above the frequency where the package and die take over.

Likely follow-up: Is staying below target sufficient? Not always: a sharp resonance below target can still ring with a repetitive load at its frequency, so the shape matters as well as the level.

Read: PDN Target Impedance: Calculation and Limitations · PDN Target Impedance Calculator · First, Second and Third Droop: PDN Frequency Regions
Try it: the target impedance panel

Short answer. Because different parts of the network supply current on different timescales. The first droop, around a nanosecond, is held up by on-die capacitance; the second, tens of nanoseconds, by package and board ceramics; the third, microseconds, by bulk capacitance until the regulator’s loop catches up.

A strong answer adds. Each droop has its own owner and its own fix: the first can only be helped on the die or in the package, the second by board decoupling and mounting, the third by bulk capacitance and the regulator’s bandwidth. Identifying which droop you are looking at is the first step in any rail problem.

Likely follow-up: Which droop does adding board capacitors help? Mainly the second; they cannot reach the first because of the inductance between them and the die.

Read: First, Second and Third Droop: PDN Frequency Regions · VRM Control-Loop Bandwidth and Load Transients · Lab C: PDN Impedance and Transient Droop
Try it: the PDN lab’s transient view

Short answer. Every real capacitor has series inductance, from its body and, more importantly, from its mounting. Its impedance falls as 1/ωC, bottoms out at its ESR at the self-resonant frequency 1/(2π√LC), then rises as ωL: above that it behaves as an inductor.

A strong answer adds. For a 100 nF part with 1.6 nH of total loop inductance the self-resonance is near 13 MHz. Above it, a larger capacitance does not help; only less inductance does, by shorter mounting, more capacitors in parallel, or capacitance closer to the load, in the package or on the die.

Likely follow-up: So is a 100 nF capacitor useless at 100 MHz? It still conducts, as an inductor of about its mounting inductance, which may or may not be low enough.

Read: Decoupling Capacitors: ESR, ESL, and Placement · LC and RLC Resonance Calculator
Try it: the decoupling panel

Short answer. Usually the mounting, not the part: the pads, the trace or via from pad to plane, and the distance from the vias to the plane pair. The capacitor’s own body contributes a fraction of a nanohenry; a poor mounting adds several times that.

A strong answer adds. Short, wide connections, vias placed at or beside the pads, two vias per pad, and a power-ground plane pair close to the surface all cut it. Reverse-geometry and multi-terminal parts reduce the body’s share too. How a board capacitor is mounted often matters more than how close it sits to the pin.

Likely follow-up: Where should the plane pair be in the stackup? Close to the surface the capacitors sit on, with a thin dielectric between power and ground.

Read: Decoupling Capacitors: ESR, ESL, and Placement · Decoupling Capacitor Mounting Inductance Calculator · PCB Stackup Design and Dielectric Selection

Short answer. As close as keeps the whole loop short, which means the pads, the vias and the plane path between capacitor and chip together, not only the distance on the layout. At high frequency it is the loop inductance, not the capacitance, that limits what the capacitor can do.

A strong answer adds. The plane pair has inductance of its own, called spreading inductance, of about µ₀·h per square: 63 pH for a 50 µm dielectric. A thin dielectric therefore makes distance cheap and a thick one makes it expensive. In a wide plane it grows only slowly with distance, which is why a capacitor a few millimetres farther away, with shorter vias and a better connection, can beat a closer one with a poor connection. Closeness matters most for the smallest, highest-frequency capacitors; bulk capacitors can sit farther back, because the band they cover is far below where this inductance matters.

Likely follow-up: What about a capacitor on the other side of the board? It is often the right place under a BGA. The price is a via through the board’s thickness, so it works best on a thin board or when a power plane sits near that side.

Read: Decoupling Capacitors: ESR, ESL, and Placement · Decoupling Capacitor Mounting Inductance Calculator · PCB Stackup Design and Dielectric Selection

Short answer. Between their two self-resonances, the smaller capacitor is still capacitive while the larger has already become inductive, and an inductor in parallel with a capacitor resonates. The result is a parallel, anti-resonant peak, higher than either part on its own.

A strong answer adds. Its height goes roughly as L/(R·C), so it falls with more resistance in the loop. Fixes are values closer together, more capacitors to lower the inductance, or deliberate damping: parts with higher ESR, or a resistor, so that the resistance approaches √(L/C). The same mechanism appears between the board and the package, and between the package and the die.

Likely follow-up: Can adding a capacitor make noise worse? Yes, if it creates or moves an anti-resonance to where the load has energy.

Read: PDN Anti-Resonance and Impedance Peaks · Chip-Package-System (CPS) Power Integrity Co-Simulation
Try it: the anti-resonance panel

Short answer. Against the target impedance, band by band: enough parallel capacitors that their combined inductance meets the target at the top of the band the board is responsible for, values spread so their resonances overlap without leaving anti-resonant peaks, and bulk capacitance to bridge down to the regulator’s bandwidth.

A strong answer adds. The count at high frequency is set by inductance, not capacitance: N parts in parallel divide the mounted inductance by about N. Values are chosen so the impedance curve stays under target with damped transitions between banks, and the result is checked in a PDN simulation that includes the planes and the package, not by a rule such as one capacitor per pin.

Likely follow-up: Why not use only the largest value that fits each footprint? Because above its self-resonance every part is an inductor, so the value hardly matters; what matters is how many there are and how they are mounted.

Read: Decoupling Capacitors: ESR, ESL, and Placement · PDN Anti-Resonance and Impedance Peaks · PDN Target Impedance: Calculation and Limitations
Try it: the decoupling panel, adding a second bank

Short answer. Enough that the capacitor, not the regulator, holds the voltage until the regulator’s loop takes over: its impedance at the loop bandwidth should equal the target, so C ≈ 1/(2π·f_bw·Z_target).

A strong answer adds. For the 1.2 mΩ target above and a regulator with a 200 kHz loop bandwidth, that is about 660 µF. It is a first estimate. The bulk parts’ ESR and ESL must also be low enough to stay under target in the band they cover; the regulator’s output impedance and phase margin shape the handover; and ceramic capacitance falls with DC bias, so the nominal value is not what you get.

Likely follow-up: What if the regulator is slower? The same step needs more capacitance, in proportion: halving the loop bandwidth doubles the capacitor.

Read: VRM Control-Loop Bandwidth and Load Transients · PDN Target Impedance: Calculation and Limitations · MLCC Derating: DC Bias, Tolerance, Temperature, Ageing
Try it: the regulator panel

Short answer. DC bias: the dielectric of class II ceramics, such as X5R and X7R, loses permittivity under an applied voltage, and a small case at a high fraction of its rating can lose half or more of its capacitance. Temperature and ageing reduce it further.

A strong answer adds. The derating depends on the part and the vendor, not just the marking, so it has to come from the vendor’s curve at the operating voltage. Class I, C0G, parts barely change, but come only in small values. A PDN designed with nominal values can miss its target in the band the bulk ceramics were meant to cover.

Likely follow-up: Do bias and temperature derating combine? Yes; they multiply, so both have to be applied.

Read: MLCC Derating: DC Bias, Tolerance, Temperature, Ageing

Short answer. A closely spaced plane pair is a low-inductance path for current and a small, very good capacitor. It is also a cavity: at frequencies where the board’s dimensions are a whole number of half-wavelengths, standing waves form and the impedance varies strongly with position.

A strong answer adds. Below the first cavity mode the planes behave as a lumped capacitance and spreading inductance; above it, where a capacitor sits relative to the standing wave decides whether it helps. Thinner dielectric, edge stitching and damping, and decoupling placed at high-impedance locations reduce the effect.

Likely follow-up: How do you estimate the first resonance? Half a wavelength across the longest dimension in the dielectric: f = c/(2·a·√D_k).

Read: Power-Plane Cavity Resonance and Edge Radiation · Power Plane Cavity Resonance Calculator

Short answer. Below the loop bandwidth the regulator actively holds the voltage, so its output impedance is low; above it, the loop cannot keep up, and what is left is the output inductor and the capacitors. The bandwidth is where the regulator hands over to the bulk capacitance.

A strong answer adds. A load step faster than the loop sees no regulator at all for its first microseconds. Too little phase margin makes the loop’s own output impedance peak. Remote sensing at the load corrects the DC drop along the way, but puts that path inside the loop, which affects stability.

Likely follow-up: Why not make the loop much faster? Switching frequency and stability limit it; the capacitors exist precisely because it cannot be.

Read: VRM Control-Loop Bandwidth and Load Transients · First, Second and Third Droop: PDN Frequency Regions
Try it: the regulator panel

Short answer. Resistance in the planes, vias, package and bumps takes a permanent slice of the voltage budget at full current, before any AC noise. Electromigration is the slow movement of metal atoms under high current density, which over years opens conductors; it is a lifetime limit, not an immediate one.

A strong answer adds. Current crowds at vias, necks and the balls nearest the source, so an average density can look safe while a few locations run far above it. Electromigration lifetime falls steeply with current density and exponentially with temperature, which is why the limit is checked at the hot spot. Both are found by a DC solve of the real geometry.

Likely follow-up: How do you fix an IR-drop hot spot? More vias or copper where the current crowds, more balls or bumps on the rail, or moving the regulator’s sense point.

Read: DC IR Drop and Electromigration

Short answer. When many outputs switch together, their currents return through the same few ground and power connections, and the inductance of those connections develops a voltage, L·N·di/dt. The local ground moves, and every signal referenced to it moves with it, including quiet ones.

A strong answer adds. It grows with the number of outputs switching in the same direction, with the edge rate and with the shared inductance. The fixes are more and shorter power and ground connections, slower edges where timing allows, data bus inversion to limit how many bits switch, and on-die decoupling.

Likely follow-up: Why does a quiet output fail? Because its reference moved under it while it was not switching.

Read: Simultaneous Switching Noise and Ground Bounce
Try it: the switching noise panel

Short answer. The return current has to move from the ground plane to the power plane at the via, and the only path between the two planes is through decoupling capacitors or the plane capacitance itself. That path has inductance, so the transition becomes a discontinuity and a coupling point.

A strong answer adds. Every signal making the same transition shares that path, so their return currents mix and inject noise into the power network, and power-network noise couples back into the signals. Stitching capacitors near the via, keeping both reference planes the same net where possible, and close plane pairs reduce it. It is where signal integrity and power integrity are one problem.

Likely follow-up: Why does a power plane work as a signal reference at all? At high frequency the return current flows on whichever plane lies nearest the trace, power or ground, because that path has the least inductance. It works when that plane is continuous under the trace, and when, wherever the signal changes layers, the return current has a nearby, low-inductance path to the other plane: a stitching capacitor, or a closely spaced plane pair.

Read: Return Current Paths: Reference Planes, Splits and Gaps · Stitching Vias and PCB Layer Transitions · Power Delivery Network (PDN) Basics: VRM to Die

Short answer. A gate’s delay depends on its supply voltage, so noise on the supply of a clock buffer or driver moves its edges in time. The sensitivity is measured in picoseconds per millivolt of supply noise.

A strong answer adds. A sensitivity of 0.12 ps/mV turns 40 mV of ripple into 4.8 ps of jitter, which is 15% of the 31.25 ps unit interval of a 32 Gb/s NRZ link. The effect accumulates along a clock tree, so a long tree on a noisy rail is the worst case. Noise inside a PLL’s loop bandwidth is partly corrected; noise on buffers after it is not. That is why sensitive clock and I/O rails are often separated and filtered.

Likely follow-up: Which noise frequencies hurt most? Those the PLL cannot track and that line up with the data’s timing, often near the PDN’s resonances.

Read: PSIJ: How Power Supply Noise Becomes Jitter
Try it: the PSIJ panel

Short answer. Put a low-pass filter between them: a ferrite bead or a small inductor in series, with a capacitor to ground on the sensitive side. It attenuates noise above its corner, but only if the filter is damped and the bead is carrying well under its rated current.

A strong answer adds. The inductor and capacitor resonate at 1/(2π√LC), and with little resistance they peak there instead of attenuating. A bead that behaves as about 1 µH at low frequency, feeding 10 µF, resonates near 50 kHz with a characteristic impedance of 0.32 Ω; with 0.1 Ω of series resistance the peak has a Q of about 3. The filter can therefore amplify noise where the regulator’s own rejection is weakest, and damping, in a lossy bead, a series resistance or a damped capacitor, is part of the design. A bead’s impedance also falls as DC current biases it, its resistance costs a DC drop, and it does nothing below its corner, which is where a regulator with good low-frequency rejection does better.

Likely follow-up: Does the filter work in both directions? Yes. It also keeps the sensitive circuit’s own current noise off the shared rail.

Read: PSIJ: How Power Supply Noise Becomes Jitter · PDN Anti-Resonance and Impedance Peaks · VRM Control-Loop Bandwidth and Load Transients

Short answer. Because the important resonances sit at the boundaries: between the board and the package, and between the package and the die. A board-only model cannot contain a resonance that involves the package’s inductance and the die’s capacitance, so it produces a smooth curve with the peak missing.

A strong answer adds. Chip–package–system analysis joins a chip power model, the package model and the board model, and drives them with the die’s real current profile. Each model arrives from a different team and at a different time, which is the practical difficulty.

Likely follow-up: What does the chip power model provide? The on-die capacitance, the grid resistance and the current profiles of the workloads.

Read: Chip-Package-System (CPS) Power Integrity Co-Simulation · Package Interconnects as Transmission Lines

Short answer. With a VNA in a two-port shunt-through arrangement: one port drives current into the rail and the other senses voltage at the same point, so the probe’s own resistance is not part of the measurement.

A strong answer adds. Common-mode isolation on the cable shields is needed, or a ground loop swamps the reading. A one-port reflection measurement cannot resolve milliohms, because a few milliohms are a tiny fraction of the 50 Ω reference. Calibrate to the probe tips, keep the probe connections short and close together, and remember that the result is the impedance at that point on the board, not at the die.

Likely follow-up: How do you measure ripple on a rail without fooling yourself? With a short ground connection at the tip, the right bandwidth, and a probe made for low-voltage rails; a long ground lead picks up its own noise.

Read: SI/PI Measurement: Probes, Fixtures and Calibration · S-Parameter De-Embedding and Fixture Removal

Short answer. Start from the requirements: each rail’s voltage, tolerance and the load’s current steps and spectrum, then derive target impedances. Plan the stackup with close power-ground plane pairs, then choose the regulator, bulk and ceramic capacitors band by band, and check DC drop and current density.

A strong answer adds. Then simulate the PDN with the package and, if available, the chip power model, against the target over frequency and in the time domain with realistic load steps; iterate placement and values; and after build, measure the impedance and ripple to correlate. Recording the assumptions and the reference points is what makes the result reviewable.

Likely follow-up: Where do the load current numbers come from? The silicon vendor’s power models and design guides, or measurement on a previous generation.

Read: Signal Integrity Simulation Workflow · PDN Target Impedance: Calculation and Limitations · PCB Stackup Design and Dielectric Selection · Simulation-to-Measurement Correlation for SI/PI

Short answer. An anti-resonance: the inductance of one stage of the network resonating with the capacitance of the next. At tens of megahertz, seen from the die, it is usually the inductance from the board capacitors through the package, against the package and on-die capacitance.

A strong answer adds. Lower down it can be two board capacitor banks; the frequency and sharpness of the peak tell you which. Check which elements resonate there with f = 1/(2π√LC). The plot was computed with 250 nF on the die and about 29 pH from the die back to the board capacitors, which gives 59 MHz. Then check the self-resonances of the banks either side. Fixes are lower inductance, damping with resistance, or capacitors that fill the gap; adding more of the same value usually only moves the peak.

Likely follow-up: Why is a sharp peak worse than a broad one of the same height? A repetitive load at that frequency builds up a large response; a well-damped peak cannot ring.

Read: PDN Anti-Resonance and Impedance Peaks · Chip-Package-System (CPS) Power Integrity Co-Simulation · Decoupling Capacitors: ESR, ESL, and Placement
Try it: the anti-resonance panel, “Two decades apart” then “Deliberately damped”

Short answer. The third droop: the bulk capacitance running out before the regulator’s control loop responds. It is not a decoupling problem at the device.

A strong answer adds. Its depth depends on the size of the step, the bulk capacitance and the regulator’s bandwidth and phase margin. More bulk capacitance, a faster or better-compensated loop, or a load that ramps more slowly all help. Board ceramics near the device will not.

Likely follow-up: What would a dip at a few nanoseconds mean instead? The first droop, owned by on-die and package capacitance.

Read: First, Second and Third Droop: PDN Frequency Regions · VRM Control-Loop Bandwidth and Load Transients

Short answer. Suspect a load current at a frequency where the PDN’s impedance peaks. Measure or estimate that workload’s current spectrum, compare it with the impedance profile, and look at the rail at the die if possible.

A strong answer adds. A loop that toggles at a fixed rate can sit right on an anti-resonance, so a modest current builds a large voltage. Confirm by changing the workload’s rate and watching the failure move, then fix by damping or moving the resonance rather than by adding capacitance blindly. Check DC drop under that workload too.

Likely follow-up: How can you see the die rail? Through on-die voltage monitors or sense points, if the silicon provides them.

Read: SI/PI Debugging: From Symptom to Cause · PDN Anti-Resonance and Impedance Peaks · PDN Target Impedance: Calculation and Limitations

Short answer. The new capacitors created or shifted an anti-resonance into the band where the load has energy, or their mounting added inductance instead of reducing it.

A strong answer adds. Plot the impedance before and after: the peak will have moved or grown. Damping, values chosen to fill the gap, or a lower-inductance mounting fixes it. Decoupling is designed against an impedance profile, not by count.

Likely follow-up: What would you change first? The damping and the mounting, before the values.

Read: PDN Anti-Resonance and Impedance Peaks · Decoupling Capacitors: ESR, ESL, and Placement