Power Integrity / 10
VRM Control-Loop Bandwidth and Load Transients
A voltage regulator holds its output steady by measuring the error and correcting it. That feedback takes time, and a digital load changes far faster than the loop can react — so for the first microsecond after a load step, the regulator is simply not participating. Its bandwidth is the frequency where it stops helping and the capacitors take over.
A feedback loop is not instantaneous
When beginners analyze a power delivery network, it is easy to view the Voltage Regulator Module (VRM) as an active throttle that continuously maintains a rock-solid output voltage. If a sudden load step causes the rail to dip, intuition suggests the regulator should immediately dial up power to compensate.
In physical reality, a switching regulator is an electro-mechanical feedback control system subject to the fundamental laws of control theory. To regulate voltage, it must sample the output rail through a sense network, compare that voltage against an internal bandgap reference, compute an error signal, and modulate the pulse-width duty cycle of its power MOSFETs through a physical output inductor. That measurement, calculation, and filtering take real time. A high-performance multiphase buck converter typically achieves a closed-loop bandwidth between 50 kHz and 300 kHz. That means the regulator is completely blind to any disturbance faster than several microseconds. During the critical initial moments after a digital transient hits, the VRM is not participating at all; the entire responsibility for keeping the rail alive rests on the passive capacitors downstream.
A switching regulator works by comparing its output against a reference and adjusting how much energy it delivers each cycle. That is a control loop, and every control loop has a bandwidth: the frequency above which it can no longer track what it is trying to correct.
Below that bandwidth, the loop is working. If the rail sags, the regulator notices and pushes harder, and the output impedance you see is low — set by the feedback, not by the hardware. Above it, the loop cannot keep up, and what is left is the raw output network: mostly the output inductor, which is an inductance, so the impedance rises with frequency.
That is why a regulator's output impedance is flat at low frequency and rises above its bandwidth. The flat part is what the loop is buying you. The rising part is what the capacitors downstream have to cover.
The loop is slower than the load
A multiphase regulator's control loop typically closes somewhere between a few tens and a few hundred kilohertz. That is fast compared with thermal events and hopelessly slow compared with a digital load step.
Be careful converting a bandwidth to a time, because three different times get quoted and they are not equal. For a single-pole response at 100 kHz the time constant is 1/(2π·100 kHz) = 1.59 µs; the 10–90% rise time is about 2.2τ = 3.5 µs; and settling to a small error band is several τ longer again. The period of 100 kHz — 10 µs — is none of these, and is the number most often quoted by mistake. A real loop is not single-pole anyway: order, damping and any peaking near crossover change the recovery shape.
Against any of those, a core waking from clock-gating changes its current draw in a hundred nanoseconds — more than an order of magnitude faster than the loop's own time constant.
And the release matters as much as the step. When a heavy load switches off, the inductor current cannot fall instantly, so the energy still in flight goes into the output capacitance and the rail overshoots — often further than the sag it just recovered from, and on a rail with a load line the whole window shifts too. Sign-off has to cover both directions.
So during the entire transient, the regulator does nothing useful. The bulk capacitors supply the charge, the rail sags, and only afterwards does the loop notice and pull it back. This division is exactly the third droop: its depth is set by the bulk capacitance and its duration and recovery by the loop.
Load-line droop is on purpose
Many rails are deliberately not regulated flat. Adaptive voltage positioning — a load line — sets the output voltage to fall in proportion to load current, so the rail sits high at light load and low at heavy load.
This looks like giving away DC accuracy, and it is, for a good reason: it centres the transient window. Coming out of a light-load state the rail is already high, so a sudden current step has further to fall before it hits the lower limit; going the other way, the overshoot on load release has more headroom. The same capacitors buy roughly twice the effective transient window. It also lowers average power at heavy load, which is a real efficiency argument on its own.
Where capacitance and stability collide
Output capacitance is not a free variable. It sits inside the control loop and moves the poles, so adding bulk capacitance to fix a droop can erode phase margin and leave a loop that rings — turning a clean sag into a damped oscillation that lasts far longer than the event that caused it. The ESR of those capacitors is part of the compensation too, which means swapping a bulk electrolytic for a lower-ESR polymer part can destabilise a loop that was tuned around it.
The practical consequence: bulk capacitor changes late in a programme are a regulator conversation, not a BOM substitution. A part that is electrically superior in isolation can make the system worse, and the symptom — a slow ring on the rail after a load release — looks nothing like a capacitor problem.
Why this decides how your board behaves
- It sets where bulk capacitance has to start working. The crossover between the regulator's rising impedance and the bulk bank's falling one is a handoff — and handoffs are where anti-resonances live.
- It cannot be raised without limit. Loop bandwidth is bounded by the switching frequency and by stability margin. You cannot simply ask for more.
- Higher bandwidth is not free. A faster loop is closer to instability, and peaking near crossover produces its own ringing on a load step. A well-damped slower loop is often better than a fast, peaky one.
- Release matters as much as application. When a heavy load switches off, the inductor current cannot fall instantly, so the energy still in flight goes into the output capacitance and the rail overshoots — often further than the sag it just recovered from.
What to do about it
Be careful converting a bandwidth into a time. Three different times get quoted and they are not equal. For a single-pole response at 100 kHz the time constant is 1/(2π·100 kHz) = 1.59 µs; the 10–90% rise time is about 2.2τ = 3.5 µs; and settling to a small error band is several τ longer again. The period of 100 kHz — 10 µs — is none of these, and is the number most often quoted by mistake.
Size the bulk bank to cover from the loop's ceiling downward. The regulator and the bulk capacitors are a relay, and the handover frequency is the loop bandwidth. Bulk capacitance that only starts working well above it leaves a gap.
Check both directions of the transient. Droop sets timing margin; overshoot sets the high-rail and reliability limit. They are different specifications and a design can pass one and fail the other — especially on a rail with a load line, where the whole window shifts.
Do not expect the loop to help with anything fast. A core waking from clock-gating changes its current in a hundred nanoseconds, more than an order of magnitude faster than a 100 kHz loop's time constant. That event is owned entirely by capacitors.
- A droop lasting microseconds. That is the loop's timescale. Anything shorter is not a regulator problem, however tempting it is to adjust the regulator.
- Ringing on the recovery. Loop peaking near crossover, or an anti-resonance between the regulator and the bulk bank. Its frequency distinguishes them — peaking rings near the crossover frequency, an anti-resonance rings at 1/(2π√LC).
- Overshoot on load release larger than the droop on application. Normal, and worth checking against the absolute-maximum rating rather than the ripple budget.
- A regulator that measures fine at its own output and badly at the load. That is IR drop and PDN impedance between the two, not a loop problem. Check where the sense point is. See IR drop.
Go deeper — what closed-loop output impedance really looks like
The useful model for PDN work is that the regulator's closed-loop output impedance is approximately resistive inside the loop bandwidth and inductive outside it:
Getting this shape right matters more than it sounds. Modelling the regulator as a plain series R + jωL from DC gives it an enormous apparent inductance at low frequency and invents a violent resonance against the bulk capacitors that no real rail has. The loop is precisely what prevents that, and a model that omits the loop omits the reason the low frequencies are quiet.
Why bandwidth is bounded. A switching converter samples its output once per switching cycle, so its loop cannot meaningfully exceed a fraction of the switching frequency — typically a tenth or so, with stability margin eating into that. Raising fsw raises the ceiling and costs switching losses and efficiency. That trade is why multiphase converters exist: interleaving raises the effective ripple frequency without raising each phase's switching losses proportionally.
A load line is a deliberate choice, not a defect. Many high-current rails regulate to a voltage that falls with load on purpose — adaptive voltage positioning. It halves the apparent transient excursion by starting high at light load, and it reduces power at heavy load. The cost is that the DC window is now load-dependent, so the static and dynamic budgets have to be evaluated together rather than separately.
In the real world
The regulator is the part of the PDN most likely to be treated as a black box with a datasheet, and most likely to be blamed for problems it cannot cause. Its loop bandwidth is a single number that settles the question: anything faster than the loop's time constant is not its doing, and no amount of compensation tuning will change that.
The other habit worth keeping is asking what the regulator is sensing. A loop regulates what it measures, and the difference between measuring at the converter and measuring at the load is the difference between a specification met on paper and one met at the transistor.