Chip-Package-System Power Integrity Co-Analysis

Why a model has to end somewhere, and why that matters

Standard engineering methodology relies on modular division: break a massive problem into independent subsystems, solve each subsystem in isolation, and integrate them at the end. In hardware development, this leads naturally to siloed teams: silicon engineers extract the on-die power grid, packaging engineers model the BGA substrate, and board engineers simulate the PCB power planes and decoupling capacitors. Each team proves their standalone subsystem meets its target impedance and signs off.

Yet when the assembled hardware powers up on the test bench, the supply rail violently oscillates and crashes the system. This happens because the die, package, and board are not decoupled islands — they are three electrically continuous impedance stages connected in series. The most dangerous anti-resonant peaks on a PDN do not exist within any single subsystem. They form precisely at the boundaries where one subsystem connects to the next. When a simulation stops at the package balls or die bumps and terminates the port in an ideal boundary condition, it mathematically erases the interface — and with it, the very resonance that will destroy the product.

You cannot simulate everything. A board PDN model has to stop at the package balls, and whatever you put there — an ideal current source, a lumped capacitor, an open circuit — is a stand-in for everything beyond.

Normally that is fine. A boundary condition only matters if something interesting happens at it. But in a PDN, the boundaries are precisely where the interesting things happen: each one sits at a handoff between two stores of charge, and a handoff is where an anti-resonance forms.

So the peak you most need to find is exactly the one your boundary condition replaced with a guess. That is the argument for co-analysis in one sentence, and everything below is detail.

Why separate models miss the answer

Simulate the board PDN alone and you must terminate it in something at the package balls. Whatever you choose — an ideal current source, a lumped capacitor, an open — is a guess about the package and die, and the impedance peak that lives at that boundary is a function of exactly that guess. The same is true one level up: a package model needs a die model to terminate into.

A PDN's significant resonances sit at handoffs between stages — a bank that has gone inductive against one that is still capacitive — so a model that stops at a handoff cannot contain the resonance that lives there. It will produce a smooth, plausible impedance curve with the peak missing, and nothing about the result looks wrong. (The converse does not hold: a handoff can be well enough damped to show no peak at all, which is what a controlled-ESR bank buys.)

What the die contributes

The die enters as a chip power model — a reduced-order network extracted from the full design, small enough to simulate but preserving what matters electrically:

On-die capacitance, both intentional decoupling and the intrinsic capacitance of every non-switching transistor. This is what holds up the first droop.
Power grid resistance, distributed rather than lumped, so IR drop appears at the right locations rather than as an average.
Current profiles per region, which is what excites the network — and the part most likely to be a placeholder early on.
Bump locations, so the die's connection to the package is spatially real rather than a single node.

The die model is the weakest link, and it arrives last Everything else in a co-analysis comes from geometry you control. The chip power model comes from the SoC team, is extracted from a design that is still changing, and lands late. Its current profile is often the roughest part of the whole simulation, and it is the part the answer is most sensitive to. Treat an early co-analysis result as a shape to design against, not a number to sign off on.

What it costs, and how to phase it

Co-analysis is expensive in the ways that matter to a schedule: model availability, extraction runtime, simulation runtime, and the coordination cost of three teams whose models have to agree on port definitions and reference planes. Running it only after the main design decisions are fixed limits how much the result can improve the design.

The workable pattern is progressive. Start with a lumped die model — a single capacitance and resistance with a plausible step current — early enough that the package and board decisions are still open; that alone locates the major resonances to within a factor that is good enough to steer stackup and decoupling. Refine to a real chip power model when it exists, and reserve full co-analysis for the specific questions that only it can answer: first-droop magnitude, SSN with on-die effects included, and the package-to-die anti-resonance frequency.

Why this decides how your board behaves

The missing peak is not visible as missing. A truncated model produces a clean curve. There is no error message and no discontinuity — just a resonance that is not there.
It is the peak that hurts. The package-to-die handoff sits in the hundreds of megahertz, which is where a modern core's di/dt has real energy.
Assign ownership across the boundary. Board, package, and die teams often own separate models, so an interface resonance can surface late unless one person owns the combined result.
Signal and power interact across it too. A driver's return current flows through the same package and board network that the PDN analysis covers, which is why SSN and PDN are the same problem seen from two directions. See Simultaneous Switching Noise and Ground Bounce.

What to do about it

Get a die model early, even a crude one. A single lumped capacitance and resistance for the on-die network is far better than an ideal source, because it at least puts a resonance somewhere near the right frequency. Precision can come later; the existence of the peak cannot be added later.

State the partition and the port definitions explicitly. Where does the board model end, where does the package model begin, and are the ports at the same physical plane with the same reference? Most co-analysis failures are bookkeeping failures, not physics ones.

Treat the current profile as the weakest input. The network can be extracted accurately; the excitation usually cannot, early on. A placeholder current profile produces a confident-looking answer to a question you have not actually asked yet.

Check that the combined model reproduces each part. If the assembled simulation does not match the standalone board model where the board dominates, the partition is wrong somewhere.

Using this to find a fault

A measured peak the simulation does not have. First suspect: the model stops at the boundary where that peak lives. Compare the peak's frequency against 1/(2π√LC) for the package inductance and the die capacitance.
Simulation and measurement agree at low frequency and diverge above ~100 MHz. Classic truncation signature. The board dominates below, the package and die above.
A result that changes a lot when you change the boundary condition. That sensitivity is itself the finding — it means the boundary is electrically active and needs a real model, not a better guess.
Noise at one block caused by another with no shared net. Transfer impedance through a shared plane or package layer. A single-port analysis cannot show it.

Go deeper — what a chip power model contains, and what co-analysis costs

The die enters as a reduced-order network — small enough to simulate, large enough to keep what matters electrically. Four things have to survive the reduction:

On-die capacitance, both intentional decoupling and the intrinsic capacitance of every non-switching transistor. This is what holds up the first droop, and the intrinsic part is often larger than the intentional part.
Power grid resistance, distributed rather than lumped, so IR drop appears at the right locations rather than as an average across the die.
Current profiles per region — the excitation, and the input most likely to be a placeholder early in a project.
Bump locations, so the die's connection to the package is at the right places. A die model with a single lumped port cannot show a gradient across the die.

What it costs. Co-analysis is expensive in ways that are worth being honest about: the models are large, they come from three organisations on different schedules, and they carry confidentiality constraints that make sharing them awkward. The full analysis usually arrives later than you want it.

Which is why the practical approach is staged. Start with crude terminations and refine them; the first version answers "is there a peak near here?" and only the last version answers "how tall is it?". Doing it in that order means the structural decisions — package inductance, on-die capacitance targets, bump map — are informed at the point they can still be changed.

One more thing the partition has to get right. Signal and power share the same physical structures, so a genuinely complete analysis is not just three PDN models joined together — it is a model in which a driver's return current and the PDN's current are the same current. That is what "chip-package-system" means in full, and it is also why the boundary between an SI model and a PI model is itself a partition with the same problem.

Practical co-simulation workflow and port setup. Setting up a chip-package-system simulation in practice requires rigorous boundary discipline to prevent artificial artifacts:

Port referencing and spatial grouping: At the board-to-package BGA boundary and package-to-die C4 bump field, never assign all power pins to a single lumped port. Group pins into localized spatial clusters referenced to their adjacent return pins. A global idealized ground reference introduces artificial return paths that artificially suppress loop inductance.
Bridging the chip power model (CPM): The die model must include both the non-switching intrinsic capacitance (C_die) and the effective grid series resistance (R_grid). Terminating the package at the bumps with an ideal current source alone is a fatal error: it omits the significant damping that the on-die grid resistance provides, leading to artificially exaggerated anti-resonant peaks that cause teams to over-design the board capacitor network.
Cascaded AC loop verification: Before attempting multi-microsecond time-domain SPICE transient simulations, perform an AC loop impedance analysis looking into the die bumps: Z_die(f) = [ (Z_board + Z_pkg) || Z_die ]. This frequency-domain sweep identifies the exact frequencies and Q-factors of boundary anti-resonances in seconds, steering layout and stackup fixes before spending days on transient convergence.

In the real world

Co-analysis is as much a procurement and scheduling problem as a technical one. The technical method is well understood; what is hard is getting three organisations to produce compatible models at a moment when the answer can still change a decision.

So the most useful thing you can do is ask for the models early and accept rough ones. A crude co-analysis at the right time beats an exact one after tape-out, because the value of the answer is entirely in what it lets you change.