Decoupling Capacitors: ESR, ESL, and Placement

Why a capacitor helps at all

In beginner textbooks, decoupling capacitors are frequently described as “filters that short high-frequency noise to ground.” While that filter model is useful in low-speed analog filtering, it misrepresents what happens on a high-speed digital rail. In a digital system, a decoupling capacitor is not a passive sponge soaking up noise — it is an active, local charge reservoir parked as close to the chip as physical layout allows.

When clock gates fire and millions of transistors switch simultaneously, they demand an immediate surge of charge within tens of picoseconds. The main voltage regulator is parked centimetres away; hindered by signal propagation delays and the series inductance of power planes, it cannot respond for hundreds of nanoseconds or microseconds. During that critical window, the decoupling capacitor stands in for the regulator, dumping its stored charge directly into the rail to keep the voltage from collapsing.

When the load suddenly demands more current, that current has to come from somewhere. The regulator is centimetres away behind a lot of inductance, so it cannot respond quickly. A capacitor sitting next to the load already holds charge, and charge that is already there can move immediately.

So a decoupling capacitor is not smoothing anything in the way the name suggests. It is a local source, standing in for the regulator over the timescales the regulator cannot reach. The question is how short a timescale it can cover.

And that is not set by the capacitance. Getting current out of a capacitor means pushing it around a loop — through the part, its pads, the vias down to the planes, along the planes, and back. That loop is an inductor, and an inductor is exactly the thing that resists a sudden change in current. The capacitor can only respond as fast as its own loop allows.

The part is an RLC

A real capacitor has three elements in series: the capacitance you wanted, the equivalent series resistance, and the equivalent series inductance. Its impedance falls as 1/ωC, bottoms out at ESR, then rises as ωL. The turning point is the self-resonant frequency:

In this example, a part used for high-frequency decoupling is inductive above roughly thirteen megahertz. Well above its series resonance, the branch impedance is increasingly set by L, so mounting-loop inductance becomes as important as the nominal value.

The inductance you built, not the one you bought

To see why layout matters more than the capacitor catalog, look at the arithmetic of a real mounting loop. Consider a standard 100 nF capacitor in an 0402 package:

• The part itself (L_part): The internal metal plates and end metallization contribute roughly 0.4 nH of equivalent series inductance (ESL). This is what you bought from the component vendor.
• The mounting loop (L_mount): The surface pads, fanout traces, the pair of vias travelling down to internal plane layers, and the small loop enclosed between power and ground vias easily add 1.2 nH. This is what you built on the PCB.

The total branch inductance is the sum: L_total = L_part + L_mount = 0.4 nH + 1.2 nH = 1.6 nH. The mounting loop contributes 75% of the total inductance. If you evaluate the self-resonant frequency with datasheet ESL alone, you would expect resonance at f_SRF = 1 / (2π √(0.4 nH × 100 nF)) ≈ 25.2 MHz. In reality, with the 1.2 nH mounting loop included, the true resonance collapses to f_SRF = 1 / (2π √(1.6 nH × 100 nF)) ≈ 12.6 MHz. At 50 MHz, the mounted capacitor's impedance is four times higher than the datasheet curve promised — entirely because of the loop you etched into the board.

The part's own ESL for an 0402 is a few hundred picohenries. The loop it sits in — pad, via down to the plane, the plane pair, and back — is routinely two to three times that. So the mounting dominates, and the levers are all layout:

• Shorten the via. The loop's area is set mostly by how far the capacitor has to reach to get to its plane pair. A power/ground pair near the surface makes every capacitor on that surface better.
• Thin the plane-pair dielectric. The two planes are the return path for each other; bringing them closer shrinks the loop directly.
• Via-in-pad, or vias at both ends. Removing the fanout trace removes real loop area. Two vias per terminal roughly halves that contribution.
• Reverse-geometry parts. An 0204 puts the terminals on the long edges, which shortens the current path through the part itself.

ESR is loss, but it also provides damping for resonances between capacitor banks. A set of very low-ESR parts produces a lower impedance floor and taller, sharper peaks between the floors. Controlled-ESR capacitors exist precisely for this, and on some rails deliberately choosing a lossier part is a practical way to flatten a curve.

Why this decides how your board behaves

• Above its SRF, the branch becomes inductive while remaining part of the network. It may no longer lower the impedance at that frequency, but its capacitance still resonates against the next stage's inductance — which is how a peak gets created. Adding parts can make a peak worse. See anti-resonance.
• Parts in parallel divide ESR as well as ESL. Lower ESR means less damping, so a bank of many low-ESR capacitors can have a higher anti-resonant peak than a smaller bank. This is why part count and impedance do not always improve together.
• Mounting can matter more than nominal value. The mounting loop typically contributes two to three times the part's own ESL, so moving a capacitor a couple of millimetres can matter more than changing its value tenfold.
• At sufficiently high frequency, the package limits support from the board. Above a few hundred megahertz in the example hierarchy, package inductance can make board capacitors much less effective at the die, increasing the importance of package and on-die capacitance.

What to do about it

Design the mounting before you choose the part. Get the power and ground planes near the surface the capacitors sit on, keep the vias short and the via pair close together, and use two vias per pad where the space exists. All of that is loop area, and loop area is the number that decides the useful bandwidth.

Thin the plane-pair dielectric. The two planes are each other's return path, and bringing them closer shrinks every capacitor's loop at once — plus it adds a little distributed capacitance for free.

Choose values from the impedance curve. Spreading parts across many decades of capacitance can introduce several anti-resonances. In this lumped example, two or three well-chosen values with suitable damping can give a flatter curve than six; confirm the choice with the mounted models and the full interconnect.

Check the capacitance you will actually get. Class II ceramics lose capacitance with applied DC bias — often half of it or more at rated voltage — and with temperature and age. A 100 nF part biased at 0.75 V may be delivering 50 nF. Use the vendor's bias curve, not the marking.

In the real world

Several familiar decoupling rules were developed for thicker boards, lower frequencies, and more inductive parts. A decade-per-value ladder, a fixed count per power pin, or placing the smallest value closest can be a useful starting heuristic, but each approximates a network whose result depends on mounted impedance and current-path geometry.

Use capacitor counts and placement rules to form an initial design, then plot the resulting impedance against the target. The curve makes resonances, damping, and mounting trade-offs visible and provides a direct basis for refining the layout.

Related

• PDN Anti-Resonance and Impedance Peaks
• PDN Target Impedance: Use and Limitations
• PDN Frequency Regions: Board, Package, and Die
• Return-Current Paths and Reference Continuity