Package & board / 01
IC Package Interconnects: Wirebond, Flip-Chip, FOWLP, Interposers, and Chiplets
A package is not just a way to get signals off a die — electrically it is an inductance in every path, and the family you choose sets how large. Two numbers decide what a package can do: the inductance per connection, and the number of connections.
Every integrated circuit begins life as a bare die of silicon: transistors fabricated on a nanometer scale, with input/output pads spaced only 40 to 80 micrometres apart. A standard printed circuit board, by contrast, is a mechanical macro-structure: surface mount pads, drill vias, and copper traces are spaced hundreds of micrometres to millimetres apart. The semiconductor package is the electromechanical bridge that translates between these two vastly different dimensional universes.
Historically, packaging was treated as little more than a protective mechanical shell — a piece of molded epoxy with metal leads to seal out moisture and conduct heat away from the die. But as digital edge rates dropped below 50 picoseconds and processor core currents escalated past 100 amperes, the package became the dominant electrical bottleneck in the entire system. Every millimetre of metal path inside the package introduces parasitic loop inductance (L) and shunt capacitance (C). On power rails, package inductance chokes transient charge delivery; on high-speed serial lanes, it forms discontinuities that cause ringing and cross-coupling.
The evolution of semiconductor packaging is therefore a relentless progression to eliminate parasitic inductance by shrinking interconnect distance: from looping wirebonds (nanohenries of inductance) to area-array flip-chip bumps (tens of picohenries), to substrate-less Fan-Out Wafer-Level Packaging (FOWLP), and finally to 2.5D silicon interposers and 3D chiplet architectures. Understanding this progression explains why modern system performance is increasingly dictated by packaging technology rather than board-level routing.
What a package has to do
A die has pads a few tens of micrometres apart. A board has features a few hundred micrometres apart, at best. A package's mechanical job is to bridge that gap — fan the connections out from die scale to board scale.
Electrically, every one of those connections is a conductor with a loop around it, which means an inductance. That inductance is in series with every signal and, more painfully, in series with every power and ground connection — where it is what stops board decoupling from reaching the die and what turns di/dt into ground bounce.
So the electrical story of packaging is almost entirely a story about that inductance: how short the connection is, how large the loop around it is, and how many of them there are to share the current.
The axis that matters
Two numbers decide what a package can do electrically: the inductance per connection and the number of connections. The first limits how fast a signal can switch and how well the PDN holds up under di/dt; the second limits how much bandwidth you can carry in parallel. Everything else — cost, thermal, mechanical — matters enormously in practice but does not change the electrical story.
| Family | Connection | Inductance | Electrically suits |
|---|---|---|---|
| Wirebond | bond wire, die edge only | high — nanohenries | low pin count, modest speed |
| Flip-chip FCBGA | bump array over the whole die | low — tens of pH | high pin count, high speed |
| FOWLP | redistribution layer, no substrate | low, and very short | thin, mobile, good PI |
| 2.5D interposer | microbump to silicon interposer | very low, very fine pitch | HBM, thousands of nets |
| Chiplets / UCIe | die-to-die, sub-millimetre reach | lowest | enormous parallel bandwidth |
Reading the table
Wirebond connects only around the die's perimeter, so the connection count scales with edge length rather than area — and every connection is a millimetre or more of thin wire, which is nanohenries. That inductance is fatal twice over: it limits signal edge rates, and it puts a hard ceiling on how fast the PDN can deliver charge. Wirebond parts have first-droop problems that no board work can touch.
Flip-chip inverts the die onto a bump array covering the whole face. Connections now scale with area, and each is a short solder bump rather than a long wire. This is the change that made wide, fast interfaces possible, and it is why the bump map is a power-integrity document as much as a signal one — the distribution of power bumps across the die face is what determines on-die IR drop and how well the die is fed under transient.
Fan-out wafer-level packaging removes the organic substrate entirely, routing on a redistribution layer built directly over the reconstituted wafer. The result is thinner and the paths are shorter, which helps both SI and PI — and is why it dominates mobile, where the total stack height is a product specification.
2.5D interposers and chiplets change the question rather than answer it better. Once connections cost almost nothing electrically and can be counted in thousands, the efficient design is a very wide, comparatively slow, very short link — the opposite of the serial-link trend. UCIe die-to-die traffic runs over reaches measured in millimetres, where loss is irrelevant and the constraints become power per bit and crosstalk density.
Why this decides how your board behaves
- It sets the inductive fence. The package inductance is what isolates board decoupling from the die above a few hundred megahertz, and therefore what makes on-die capacitance necessary. See the three droops.
- It sets how many pins can switch together. SSN is L·di/dt across a shared inductance, so the power and ground pin count — and their distribution among the signals — decides how wide a bus can be.
- It is a discontinuity in every channel. The package's trace, via and bump form part of the channel, and their impedance is rarely the board's.
- It constrains the board before the board exists. Ball pitch decides the escape problem, which decides layer count, which decides thickness, which decides via stubs.
What to do about it
Treat pin assignment as an electrical decision. Distributing power and ground among the signals rather than clustering them reduces the shared inductance every signal sees. This is decided very early and is nearly free at that moment.
Ask for the package model before you need it. A channel simulation without one is missing a real discontinuity, and a PDN simulation without one is missing the resonance that matters most.
Push back on pitch if you can. A finer pitch is a mechanical and cost decision that lands on the board as via-in-pad, more layers, or both. It is worth being in that conversation.
- Ground bounce that scales with the number of simultaneous outputs. Shared package inductance. Look at the power and ground pin distribution, not at the board.
- A PDN resonance in the hundreds of megahertz. Package inductance against on-die capacitance. No board component is inside that loop.
- A channel discontinuity that TDR places inside the package. Compare the package model's impedance with the board's — they are often deliberately different, and the transition costs something.
Go deeper — where each family's inductance comes from
The differences between families are geometric, and once you see the geometry the numbers follow.
- Wirebond connects the die edge to the substrate with a bond wire that arcs up and over. It is long, thin and far from its return, so the loop is large — nanohenries. And only the die's perimeter is available, so connection count scales with perimeter rather than area.
- Flip-chip turns the die over and connects it through an array of bumps across its whole face. Each bump is short and has a nearby return, so the inductance is tens of picohenries — two orders of magnitude better — and the count scales with area.
- Fan-out wafer-level packaging replaces the substrate with a redistribution layer built directly on the reconstituted wafer. Shorter still, and thinner, which is why it dominates mobile.
- 2.5D interposers put two dies on a shared silicon carrier with very fine wiring between them, which is how very wide, very short die-to-die interfaces become possible at all.
The pattern worth extracting: every step in this progression shortens the connection and brings its return closer. That is the whole electrical evolution of packaging, and it is driven by the same L·di/dt that drives everything else.
One consequence that surprises people: a flip-chip package's advantage is not only per-pin. Because the connections cover the die's area rather than its edge, you can afford far more power and ground bumps, and the shared inductance falls faster than the per-pin number alone suggests.
In the real world
Package choice is usually made on cost, thermal and mechanical grounds, and the electrical consequences arrive as constraints rather than as options. The useful posture is therefore to know what each family implies and to get that into the decision early, rather than to expect to choose on electrical merit.
The other thing worth doing early is asking who owns the package model and when it will exist. It is the piece of the chain most likely to be missing when the first serious simulation is run, and its absence hides exactly the resonances that matter.