PCB Stackup Design and Dielectric Selection

When designing a high-speed circuit board, the most consequential architectural decisions happen before the CAD engineer routes a single net. You cannot define the geometry of a 50 Ω single-ended line or a 100 Ω differential pair without first knowing the dielectric thickness and relative permittivity (D_k) of the core beneath it. You cannot establish clean, continuous return current paths without committing to where solid reference planes live. And you cannot control through-hole via stub lengths without fixing the board's total vertical thickness.

The PCB stackup is the master vertical blueprint of the board: the exact recipe of copper foils, prepreg bonding sheets, and hardened core laminates pressed together under heat and pressure. It dictates the physical foundation for every transmission line parameter across the entire design. If a stackup is constructed poorly — with split planes, floating reference boundaries, or high-loss dielectric resins — no amount of length tuning or serpentine routing in layout can restore the lost signal integrity.

Furthermore, a stackup is an unyielding compromise between electromagnetic physics and mechanical manufacturing. An electrically ideal stackup might pack dozens of thin dielectric layers to squeeze out crosstalk and minimize via loop inductance. But if the copper distribution is mechanically asymmetric across the central core, the board will warp like a potato chip during infrared reflow soldering, fracturing BGA joints and destroying factory yield. Designing a successful stackup is about balancing this multi-variable equation early.

What a stackup actually is

A multilayer board is copper layers separated by insulating layers, pressed together. The stackup is the recipe: how many copper layers, how thick each one is, what insulator sits between them and how thick that is, and what each copper layer is for — routing, or a solid plane.

That recipe is not an implementation detail. Every electrical property on this site traces back to it: impedance comes from trace width over dielectric height, loss from the laminate, crosstalk from spacing and height, return paths from where the planes are, and via stubs from total thickness.

And it is decided first. You cannot route until you know what layers exist, which means the stackup is committed before anyone has seen a real routing problem.

Layer count is a reference-plane count

Estimating how much routing fits on each layer is a useful starting point, but reference planes also set the layer count. Every high-speed signal layer needs a solid reference plane immediately adjacent to it, because that plane is where the return current runs — and layers you add for references cost as much as layers you add for routing.

Symmetry is the second constraint and it is mechanical rather than electrical. An asymmetric build warps during lamination as the resin cures, and a warped board does not assemble. So layers come in balanced pairs around the centre, which is why stackups jump 4, 6, 8, 10 rather than moving one at a time.

The pairing question Two signal layers between one pair of planes saves a layer and creates broadside coupling between the two signal layers, which is far stronger than edge coupling. It is acceptable if the two layers route orthogonally, and it is a crosstalk problem if they run parallel over any distance. Deciding this in the stackup — rather than discovering it in routing — is what makes the difference.

Dielectric height does three jobs at once

The distance from a trace to its reference plane is the most powerful single number in the stackup, because it sets three things simultaneously:

Impedance. Closer to the plane means more capacitance and lower Z₀, so a thinner dielectric needs a narrower trace for the same impedance — and a narrower trace has more conductor loss.
Crosstalk. Coupling between neighbours falls steeply as the plane gets closer, because the field is pulled down to the reference instead of sideways. Halving the height roughly quarters the coupling.
Return path quality. A closer plane is a tighter loop for every via and every decoupling capacitor referenced to it.

That is a genuinely good trade in dense designs: thin dielectric, narrow traces, tight spacing, more loss but far less crosstalk. On a long lossy channel the trade reverses — you want a thick dielectric and a wide trace to keep conductor loss down, and you buy the isolation with space instead.

When the material actually matters

Dielectric loss scales linearly with frequency while conductor loss scales as its square root, so they cross somewhere between 1 and 5 GHz for common laminates. Below the crossover the geometry dominates and an expensive laminate buys very little. Above it, D_f is the largest single lever available — moving from a mid-loss material to a low-loss one can more than halve the dielectric term.

Two other material properties earn their place on the specification at high speed. Copper foil roughness, because once the skin depth is under a micron the surface profile adds real loss — this is why VLP and HVLP grades are called out explicitly. And glass style, because a spread or mechanically-flattened weave is what prevents the two halves of a differential pair sitting over different amounts of glass and arriving skewed.

Why this decides how your board behaves

Dielectric height does three jobs at once. It sets impedance with width, it sets how tightly the return current is held under the trace, and it sets crosstalk. Those cannot be traded independently — halving the height quarters the coupling and needs a narrower trace, which raises conductor loss.
Total thickness sets your via stub problem. A thick board puts stub resonances in band; a thin one does not. See vias.
Plane pair spacing sets PDN behaviour. Thin plane pairs add distributed capacitance, lower the cavity's impedance, and shorten every decoupling capacitor's mounting loop.
Layer count is a reference-plane count. Every high-speed signal layer needs a solid plane adjacent to it, so planes cost layers just as routing does.

What to do about it

Start from the constraints that cannot move. Total thickness from the mechanical design, the number of routing layers from the escape problem, and the loss budget from the channel budget. Those three usually determine most of the stackup before any preference is expressed.

Give every high-speed layer an adjacent solid plane, and know which one. Not "there is a plane two layers away" — adjacent, and solid under the whole route.

Decide broadside pairs deliberately. Two signal layers between one plane pair saves a layer and creates broadside coupling between them. That is acceptable if the two layers route orthogonally or carry unrelated signals, and expensive if they carry a bus.

Specify impedance, not width, and specify the foil. Width is the fab's variable. Foil roughness is yours, and a low-loss resin on rough foil throws away much of what you paid for.

Using this to find a fault

Impedance right on some layers and wrong on others. Check what each layer is actually referenced to. A signal layer referenced across a split, or two dielectrics away, has an impedance that the intended stackup calculation did not cover.
Crosstalk worse on one layer than another with identical spacing. Different dielectric height. Coupling scales with height far more strongly than with spacing.
A channel with more loss than the laminate explains. Foil roughness, often unspecified and therefore whatever the fab had.
Boards that warp or fail assembly. Asymmetry. The build has to be balanced about the centre, which is why layer counts jump in twos.

Go deeper — why symmetry is mandatory, and what a layer really costs

Symmetry is mechanical, not electrical. An asymmetric build warps during lamination as the resin cures and shrinks, because the stresses above and below the centre do not balance. A warped board does not assemble reliably. This is why layer counts go 4, 6, 8, 10 rather than moving one at a time, and it is a constraint no electrical argument overrides.

What a layer costs. More than its area. Each additional layer pair adds lamination cycles and yield risk, adds thickness — which lengthens every via stub — and on a sequential build adds significant cost. So the pressure to reduce layer count is real, and the usual casualty is a reference plane, which is exactly the wrong thing to remove.

The height trade, stated properly. Moving a signal layer closer to its reference:

needs a narrower trace for the same impedance, which raises conductor loss;
reduces crosstalk roughly with the square of the height;
tightens the return current distribution, making the design more tolerant of small plane imperfections;
and reduces the loop area of every via transition on that layer.

Three of those are improvements and one is a cost, which is why the usual answer is to go as thin as the loss budget allows. On a low-loss build where you are conductor-limited rather than dielectric-limited, that trade tightens considerably — see loss mechanisms.

Laminate material selection: the D_f hierarchy. The dielectric loss of an interconnect scales directly with frequency and the laminate's dissipation factor (D_f = tan δ): α_d ∝ f · √D_k · D_f. Selecting the right resin system is an explicit trade between bill-of-materials cost and reach:

Standard FR-4: D_f ≈ 0.015 to 0.020, D_k ≈ 4.2 to 4.5. Lowest cost, high moisture absorption. Acceptable for low-speed digital, DC-DC power converters, and traces carrying less than 3 Gbps over short distances. At 10 Gbps and above, its steep dielectric attenuation completely closes the eye.
Mid-Loss Laminates (e.g. Isola FR408HR, Nelco N4000-13): D_f ≈ 0.008 to 0.010, D_k ≈ 3.6 to 3.8. Cost-effective workhorse for PCIe Gen 3 and Gen 4 channels up to 6–10 inches, and standard DDR4/DDR5 routing.
Low-Loss / Ultra-Low-Loss (e.g. Panasonic Megtron 6, Isola Tachyon 100G): D_f ≈ 0.002 to 0.004, D_k ≈ 3.0 to 3.4. High-performance polyphenyl ether (PPE) resin systems. Mandatory for PCIe Gen 5/Gen 6 (32 to 64 GT/s), 56G/112G PAM4 Ethernet, and multi-board backplanes. They feature extremely flat D_k stability across frequency, minimizing phase dispersion.

Copper foil roughness: why smooth copper matters more than low D_f. At gigahertz frequencies, the skin effect forces current to flow within a microscopic surface layer (δ = 1 / √(π f μ σ) — less than 0.66 μm deep at 10 GHz). To ensure copper foil bonds mechanically to resin, foil manufacturers chemically treat the surface with microscopic dendrites ("teeth"). If the tooth height is comparable to or larger than the skin depth, the current is forced to follow the undulating contours of the tooth profile, drastically increasing the effective path length and raising high-frequency conductor loss by 200% to 300%:

Standard Electrodeposited (STD/ED) Copper: Mean tooth roughness R_z ≈ 6 to 10 μm. Severe conductor attenuation above 3 GHz; unsuitable for high-speed channels.
Very Low Profile (VLP) / Reverse Treated Foil (RTF): R_z ≈ 2 to 3 μm. The practical baseline for modern enterprise boards operating between 5 and 16 GHz.
Hyper Very Low Profile (HVLP / Profile-Free): R_z < 1.0 μm. Nearly mirror-smooth copper. Essential for 28 Gbps+ and 112G PAM4 designs. At these speeds, switching from standard foil to HVLP often saves more decibels than upgrading to a more expensive low-loss dielectric.

And the glass weave. Laminate is woven glass bundles impregnated with cured resin, and the two materials have starkly different dielectric constants (glass D_k ≈ 6.0, epoxy resin D_k ≈ 3.0). In loose, open weaves (like standard 106 or 1080 glass styles), one trace of a differential pair can route directly over a dense glass knuckle while its twin runs over an open, resin-rich cavity. That differential D_k delta causes propagation velocity skew within the pair, converting differential signal energy into destructive common-mode noise. Modern stackups specify spread-glass fabrics (such as 1067, 1078, or 3313 styles) whose yarns are mechanically flattened in both warp and fill directions, eliminating the open windows and providing a homogeneous dielectric constant across the board.

In the real world

The stackup is the highest-leverage document in a board project and frequently the least reviewed. It is often produced by the fabricator from a thickness target and a layer count, and returned as a fait accompli that the signal integrity engineer sees after routing has started.

Getting into that conversation early is worth more than any amount of later optimisation, because almost nothing in it can be changed once layout is underway — and the things that cannot be changed are exactly the ones that decide whether the channel closes.