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Decoupling Capacitor Mounting Inductance Calculator
A decoupling capacitor never reaches the planes on its own: current leaves one pad, runs down a via, across the plane and back up another. That loop has inductance, and it adds to the part's own ESL — often doubling it. This calculator gives the via pair's share, which is the part that layout controls most directly.
Reading the numbers
- Bring the vias closer and the loop shrinks: the inductance falls with the logarithm of the pitch.
- Shorter vias — planes nearer the capacitor's layer — cut it in proportion. That is why decoupling capacitors belong on the side nearest their planes.
- Compare the two self-resonances: the gap between them is what mounting cost.
Every value is in the address bar as you change it, so a link reproduces the calculation exactly.
Type values with SI prefixes — 100n, 2.2p, 16G — or
drag the sliders; a bare number keeps the prefix already shown.
The formulas
Go deeper — assumptions, how it is checked, and sources
Assumptions. The via pair only. The pads, any trace between pad and via, and the spreading inductance of the planes are left out, and on a real board they are often comparable to the vias. So this is a lower bound on mounting inductance, and the right tool for comparing via placements, not for a sign-off number.
How it is checked. The model is K.viaLoopInductance, the same one the
via pages use. It is linear in via length, vanishes as the vias touch, and matches the thin-wire
approximation (μ0h/π)·ln(2s/d) within 1% once the pitch is ten diameters.
Source. C. R. Paul, Inductance: Loop and Partial, Wiley, 2010, ch. 5.