SIPI

Interface sign-off / 02

PCIe 4.0 and 5.0 Signal Integrity: Loss and Equalization

By Geetansh Arora — Principal SI/PI Engineer10 min

PCIe is the serial link the rest of the site's machinery was built for: one differential pair per lane, clock embedded in the data, and a receiver with real equalisation. Each generation doubles the rate, which doubles the frequency the channel must survive — and because loss climbs steeply with frequency, each step has been harder than a factor of two.

Link equalisation · negotiated, not designed
the channel is characterised at run time, not at design time Phase 0bothenter at 8 GT/sPhase 1upstreamset safe presets Phase 2downstreamsweeps Tx presetsPhase 3upstreamsweeps back who does what Tx: 11 presets pre-shoot + de-emphasis handles PRE-cursor Rx: CTLE analogue peaking lifts crosstalk too Rx: DFE exact cancellation handles POST-cursor none of them can fix a via-stub notch — the energy is gone, not attenuated
At 32 GT/s the eye is fully closed at the receiver pad, and that is the design point. With roughly 36 dB end to end at 16 GHz, the 16 GHz content of the signal arrives at about one part in sixty. That is a statement about one frequency, not about the waveform: the low-frequency content is barely attenuated, so what reaches the pad is not a small copy of what was launched but a smeared one, and the eye closes from dispersion rather than from uniform shrinkage. Whether it closes at all depends on the full complex channel, the transmitted spectrum and the receiver — which is exactly why a single loss number cannot predict an eye, and why the link is built around reconstructing the waveform rather than preserving it. The work is split deliberately. Pre-cursor is the transmitter's problem, because only the transmitter knows the future; post-cursor belongs to the receiver's DFE, because it can cancel exactly rather than amplify. And rather than fixing any of it at design time, the two ends run a defined negotiation at link-up, sweeping presets and reporting back until they converge on a combination that works for the channel actually present. Where the margin really goes at Gen 5 is via stubs. A 200 mil stub on a thick board resonates near 7.4 GHz — inside the band — and no equaliser setting recovers it, because at the bottom of a notch there is nothing left to scale.

PCI Express (PCIe) is the universal computational fabric connecting server processors to graphics processing units (GPUs), NVMe solid-state storage, and high-speed network interfaces. For earlier generations, standard PCB design practices and modest FR-4 laminates were sufficient. But with PCIe Gen 4 (16 GT/s) and Gen 5 (32 GT/s), NRZ signalling was pushed to its absolute physical limits over copper.

At Gen 5's 32 GT/s, the unit interval shrinks to an astonishing 31.25 picoseconds, establishing a Nyquist frequency of 16 GHz. Across an enterprise motherboard — spanning CPU package BGA vias, 12 to 14 inches of PCB trace, a standard Card Electromechanical (CEM) card-edge connector, and an add-in card — total insertion loss reaches 36 dB. At 16 GHz, less than one part in sixty of the launched signal amplitude reaches the receiver pins. The eye diagram at the receiver pad is not just degraded; it is completely, 100% closed shut.

To make a 36 dB channel functional, PCIe does not rely on passive routing margin alone. It operates as an actively negotiated, co-optimized communication system: an automated hardware state machine sweeps transmitter equalization presets, tunes receiver continuous-time filters (CTLE), and trains multi-tap decision feedback equalizers (DFE) at boot. Understanding how this equalization negotiation works and how the 36 dB budget is partitioned across real system form factors is the foundation of high-speed PCIe board design.

What "serial with an embedded clock" buys and costs

A parallel bus sends a clock alongside the data. A serial link does not — the receiver recovers timing from the data's own transitions, using a clock-and-data-recovery loop.

That removes the hardest problem a wide bus has: skew between a clock and many data wires. With one pair, there is nothing to skew against. It is why serial links scale to rates a parallel bus cannot reach on the same copper.

The cost is that everything now has to survive on one pair. There is no strobe to cancel common-mode delay, the data must contain enough transitions for the loop to track — which is what the encoding is for — and the receiver has to do real work to recover a signal the channel has badly degraded.

What it is

A differential serial link, NRZ, at 16 GT/s for Gen 4 and 32 GT/s for Gen 5, with 128b/130b encoding and an embedded clock. The unit interval is 62.5 ps at Gen 4 and 31.25 ps at Gen 5, and the Nyquist frequencies that matter are 8 GHz and 16 GHz. Each doubling of rate doubles the frequency at which the channel has to behave, which is why each generation has been harder than the last by more than a factor of two.

The channel

A realistic system channel is a package, a board escape, several inches of trace, at least one connector, an add-in card, and another package. Every one of those contributes loss and at least one discontinuity. The commonly quoted end-to-end budgets are roughly 28 dB at Gen 4's 8 GHz and 36 dB at Gen 5's 16 GHz, with the split between system board, connector and add-in card set by the CEM specification rather than by the base spec — the base spec defines the electrical layer, CEM defines the form factor's share of it.

Treat those two numbers as sizing figures, not as quotations. Each belongs to a particular specification edition and a particular reference plane, and they are repeated widely enough that the qualifications fall off in transit. Before one goes into a budget you are going to defend, take it from the base or CEM document for the revision you are building to — and note that a single number at Nyquist is a screening check, not a description of what the whole waveform experiences.

Thirty-six decibels means the signal at the receiver pad is roughly one part in sixty of what was launched. The eye there is fully, unambiguously closed. That is not a failure; it is the design point.

How the link recovers it

Equalisation is split across both ends and negotiated at link-up rather than fixed:

Where the margin actually goes at Gen 5 Via stubs. At 16 GHz Nyquist, a 200 mil stub on a thick board resonates at around 7.4 GHz — inside the band — and puts a notch in the channel that no equaliser can undo, because the energy at that frequency is gone rather than attenuated. Backdrilling moves from optional to near-universal practice across these generations — but it is an implementation remedy for a particular stackup and stub length, not something a specification mandates. A thin board may need none of it; a thick backplane may need it at Gen 3. The other large terms are connector footprint discontinuities and crosstalk from neighbouring lanes in the escape.

Sign-off

Channel compliance is statistical rather than time-domain. PCI-SIG's reference flow takes the channel's S-parameters, applies a defined reference transmitter and receiver equaliser, and computes an eye at a target bit error rate of 10−12 — far below anything a bit-by-bit simulation could reach in reasonable time. The output is an eye height and width at that BER, checked against a mask.

Two habits matter here. Check the S-parameter file for passivity and causality before trusting any of it — a non-causal file produces eye openings that do not exist. And when the budget will not close, the honest options are a lower-loss laminate, a shorter channel, or a retimer; adding equaliser strength past the reference model is a way of passing a simulation rather than a link.

Sources

Why this decides how your board behaves

What to do about it

Budget by row and name the owner of each. Package, breakout, board, connector, add-in card, far package. The breakout is the row people forget.

Attack discontinuities before attacking loss. Loss is equalisable and predictable; reflections and resonances are neither. Vias, launches and connector footprints first.

Design the stackup for the stub, not just the impedance. Board thickness decides whether a stub resonance lands in band, and exit-layer choice is free where backdrilling is not.

Report adapted equaliser settings, not eye photographs. What the receiver converged to, and how much range it had left, is the margin information.

Using this to find a fault
  • A link that trains but reports poor margin. Read the adapted settings. Coefficients sitting at their limits mean the channel is outside what the reference equaliser was defined against.
  • Deep narrow null in S21. Invert the stub formula and compare with the board's thickness and the exit layer. See vias.
  • Regular ripple in S21. Two reflecting structures; the ripple period gives their separation.
  • Works on one slot and not another. Compare the breakout and the connector launch, not the trace lengths.
Go deeper — what doubling the rate actually costs, and where the sourced numbers stop

LTSSM link equalization training and presets (P0–P10). Because high-speed channels vary widely in trace length and materials, PCIe does not hardcode transmitter settings. Instead, the Link Training and Status State Machine (LTSSM) executes an automated four-phase hardware handshake at link-up (Recovery.Equalization):

  • Phase 0 & 1: Downstream and upstream ports establish basic bit lock at 32 GT/s and advertise starting transmitter presets (typically Preset 4, 5, or 7).
  • Phase 2: The downstream port (e.g. the add-in card) fine-tunes the upstream port's transmitter (the CPU/host). The card's receiver measures incoming eye quality (using eye height/width monitors or internal BER counters) and commands the host to step through different FFE coefficients until the optimal setting is locked.
  • Phase 3: The host repeats the identical optimization process in reverse, tuning the add-in card's transmitter.

The specification standardizes 11 discrete FIR coefficient presets:

  • Preset 0 (P0): Flat output, 0 dB preshoot, 0 dB de-emphasis. Useful only for ultra-short chip-to-chip connections.
  • Preset 4 (P4): 0 dB preshoot, -2.2 dB de-emphasis. The universal starting point for link training.
  • Preset 7 (P7) & Preset 8 (P8): Aggressive equalization (P7: -6.0 dB de-emphasis, 3.5 dB preshoot; P8: -3.5 dB de-emphasis, 3.5 dB preshoot). Mandatory for long-reach 36 dB channels to boost high-frequency transitions before entering the lossy board.

Loss budget partitioning: CEM vs. OCP/EDSFF topologies. The PCIe Base Specification defines the total 36 dB electrical envelope at 16 GHz, but the physical form factor determines how those decibels are divided:

  • Standard PCIe CEM (Desktop/Server Expansion Slot): 36.0 dB total budget. Allocated as: TX package (3.5 dB), motherboard trace + breakout vias (17.0 dB), PCIe CEM card-edge connector (1.5 dB), Add-in Card trace (9.5 dB), RX package (3.5 dB), and AC coupling / board parasitics (1.0 dB). This leaves roughly 12 to 14 inches of motherboard routing on mid-loss laminates.
  • OCP NIC 3.0 / EDSFF Enterprise Storage Form Factors: These high-density enterprise form factors replace the bulky legacy CEM connector with high-performance mezzanine connectors (such as 4C+ or EDSFF E1/E3 interfaces). These connectors exhibit lower parasitic inductance and lower reflection loss (≈ 1.0 dB), and daughtercards are physically much shorter (consuming only 4 to 6 dB). This frees up an additional 3 to 5 dB of budget, allowing motherboard designers to route longer server traces or utilize more cost-effective PCB dielectric materials without compromising the 36 dB ceiling.

In the real world

PCIe is the interface where the whole toolchain gets exercised: S-parameters, channel simulation, AMI models, compliance masks and a receiver that adapts. It is also where the gap between a channel that meets its budget and a link that works is smallest, because the specification's assumptions are unusually explicit.

The part that still surprises people is how much of the margin lives in structures rather than in trace length — the breakout, the vias, the connector launch. Inches are easy to count and discontinuities are easy to overlook, and the budget is usually lost to the second.

Related

Sources

Rows marked with a claim id are tracked in the claim ledger, which records what each source can and cannot establish.