SIPI

Interface sign-off / 03

PCIe 6.0 Signal Integrity: PAM4, FLIT, and FEC

By Geetansh Arora — Principal SI/PI Engineer9 min

Gen 6 keeps the symbol rate and doubles the data rate by sending two bits per symbol. That means the channel sees the same Nyquist frequency as Gen 5, which is the central bandwidth benefit, but the receiver now has to resolve four levels instead of two, and the raw error rate that results is high enough that forward error correction stops being optional.

PAM4 · the same Nyquist, a third the eye, and FEC in the budget
what did not change Nyquist stays at 16 GHz so the channel work is familiar: same insertion loss budget, same intolerance of via stubs, same connectors 32 Gbaud carrying 64 Gb/s — two bits per symbol what it cost NRZ PAM4 −9.5 dB three eyes in the swing that held one and they are not identical — Tx linearity is now specified and the fix that changes sign-off raw BER ~1e−6 FLIT + FEC delivered 1e−12 and better a raw error every ~16 µs at 64 GT/s — measurable so the bathtub is acquired, not extrapolated six decades precoding breaks DFE error bursts, which is what a lightweight FEC handles worst
Gen 6 doubles the rate without doubling the frequency the channel must carry. Two bits per symbol means 64 GT/s uses the same 32 Gbaud — and therefore the same 16 GHz Nyquist — as Gen 5's NRZ. An NRZ implementation at the same transfer rate would need 32 GHz, where practical copper channels have much greater loss. PAM4 instead introduces an amplitude cost of 20·log₁₀(3) ≈ 9.5 dB before its additional error events. The standard addresses this with a raw error rate near 10−6 and FEC. At that raw BER, an error occurs about every 16 microseconds, making direct bathtub acquisition more practical than at much lower BER targets.

When the PCI-SIG standards body began drafting the specification for PCIe Gen 6 (64 GT/s), the industry ran directly into the physical limits of copper interconnects. Had Gen 6 followed the historical precedent of simply doubling the NRZ clock rate, it would have required a 64 GBaud symbol rate and a 32 GHz Nyquist frequency. At 32 GHz, standard server PCB laminates, via breakouts, and card-edge connectors exhibit more than 60 dB of insertion loss over typical chassis distances — an attenuation so massive that a signal could not even cross from a CPU to an adjacent expansion slot.

To preserve standard server reach without forcing an industry-wide transition to exotic, high-cost optical cables, PCIe Gen 6 enacted the most radical architectural disruption in the standard's history: it abandoned binary NRZ and adopted Pulse Amplitude Modulation 4-Level (PAM4). By packing two bits into each electrical symbol, Gen 6 delivers 64 GT/s while operating at the exact same 32 GBaud symbol rate and 16 GHz Nyquist frequency as Gen 5. The channel's frequency response sees no increase in loss.

However, compressing four voltage levels into the same total swing extracts a punishing penalty: an immediate 9.54 dB signal-to-noise ratio (SNR) reduction and extreme vulnerability to driver non-linearity. For the first time, PCIe deliberately abandons an "error-free" raw physical layer, accepting a raw bit error rate of roughly 10-6 and relying on a lightweight Forward Error Correction (FEC) engine, 1b/1b precoding, and fixed 256-byte FLIT architecture to guarantee enterprise reliability.

Why the rate could not simply double again

Every previous PCIe generation doubled the data rate by doubling the symbol rate. Gen 5 runs at 32 GT/s NRZ, so Gen 6 the same way would mean 64 Gbaud and a 32 GHz Nyquist.

Channel loss at 32 GHz is not something a connectorised copper channel of useful length can survive. Not "difficult" — the reach would collapse to something that does not reach a slot.

So Gen 6 changes the modulation instead. Four voltage levels, two bits per symbol, the same 32 Gbaud symbol rate, and therefore the same Nyquist frequency as Gen 5. The channel's job does not get harder. The receiver's does.

The trade PAM4 makes

PAM4 encodes two bits in four voltage levels, so 64 GT/s is carried at the same 32 Gbaud symbol rate as Gen 5's 32 GT/s NRZ — and therefore at the same 16 GHz Nyquist frequency. Doubling the rate with NRZ would instead require a 32 GHz Nyquist frequency, where loss can become prohibitive for a copper channel of useful length.

The tradeoff appears in amplitude. Three eyes have to fit in the swing that previously held one, so each eye is a third the height:

SNR penalty = 20·log10(3) ≈ 9.5 dB Before accounting for the extra transitions and the additional error events PAM4 introduces, which push the practical penalty higher still. Nine and a half decibels is a large fraction of a channel budget to give away at the start.

There is a second, subtler cost: the three eyes are not identical. Level-dependent nonlinearity in the driver makes the outer eyes and the inner eye behave differently, so transmitter linearity becomes a specified parameter in a way it never was for NRZ.

Why FEC becomes mandatory

Nine decibels of lost amplitude cannot be recovered from the channel, so Gen 6 changes the target instead. The raw bit error rate is relaxed to around 10−6, and forward error correction brings the delivered rate back to 10−12 and better. FEC is no longer a protocol nicety — it is a term in the electrical budget, and the link is designed knowing the correction is there.

That requires a fixed-size transport to carry the code words, which is what FLIT mode provides: fixed-length flow control units with FEC and CRC in known positions. Gen 6 is FLIT-only, and a Gen 6-capable link uses FLIT mode at lower rates too.

Precoding completes the picture. A DFE that makes a wrong decision feeds that error back and can produce a burst, and burst errors are exactly what a lightweight FEC handles worst. Precoding at the transmitter breaks the correlation so DFE errors arrive isolated rather than clustered, which is what makes the correction budget work.

The change that most affects day-to-day work A raw BER of 10−6 is measurable. At 64 GT/s that is an error roughly every 16 microseconds — a bathtub curve you can actually acquire rather than extrapolate. Gen 6 quietly removes the largest source of uncertainty in serial link sign-off: no longer fitting Gaussian tails six decades below anything observed, but measuring the real distribution and letting FEC cover the rest.

What stays the same

Because Nyquist has not moved, the channel work is familiar: the same 16 GHz insertion loss budget, the same intolerance of via stubs, the same connector and escape discontinuities. What changes is how little margin there is to absorb any of it, and how much more a reflection or a crosstalk aggressor costs when it lands on an eye a third the size.

Sources

Why this decides how your board behaves

What to do about it

Re-budget noise, not just loss. The temptation is to reuse a Gen 5 channel because Nyquist did not move. The loss budget survives; the noise budget does not.

Check all three eyes. They are not identical — transmitter level linearity and threshold placement affect them differently — and reporting one number for a PAM4 link is incomplete.

Separate raw and post-correction error rates in every report. Quoting one as the other is the most common confusion on this topic.

Look for sources of bursty errors specifically. DFE error propagation and periodic aggressors produce exactly the structure FEC handles worst.

Using this to find a fault
  • One eye much worse than the other two. Level linearity or threshold placement — a device issue, since the channel treats all three alike.
  • Post-FEC errors with an acceptable raw rate. Bursts. Look at error spacing, not just error count.
  • A channel that was comfortable at Gen 5 and marginal at Gen 6. Check crosstalk and return loss before loss, since loss is the one thing that did not change.
Go deeper — the mechanisms Gen 6 adds, and what they are each for

1b/1b Precoding: breaking DFE error bursts. In a high-speed PAM4 receiver, the decision feedback equaliser (DFE) slices the incoming waveform among three stacked eyes. If random noise causes the slicer to pick the wrong level, the erroneous decision feeds back into the summer with inverted polarity. This feedback frequently triggers an extended burst of successive symbol errors.

A lightweight FEC code has a strictly bounded burst-correction capability; a sustained burst of 8 or 16 consecutive corrupted symbols will overwhelm the decoder and trigger an uncorrectable frame drop. To eliminate this hazard, PCIe Gen 6 introduces a 1b/1b precoder at the transmitter: y[n] = x[n] ⊕ y[n-1]. The receiver applies the inverse operation: x[n] = y[n] ⊕ y[n-1]. Mathematically, this decimation converts an extended run of consecutive feedback errors into exactly two bit errors (one at the start of the burst and one at the end), instantly truncating the burst into isolated errors that the FEC effortlessly corrects.

The 256-Byte FLIT and Low-Latency FEC. Prior PCIe generations operated with variable-length Transaction Layer Packets (TLPs) wrapped in 128b/130b sync headers. FEC, however, requires a fixed, deterministic block size to compute parity over. Gen 6 therefore scraps variable framing and mandates a rigid 256-byte Flow Control Unit (FLIT) architecture across all packet types:

  • Payload: 236 bytes of TLP data, 6 bytes of Data Link Layer protocol headers.
  • CRC (Cyclic Redundancy Check): 8 bytes of robust error detection.
  • FEC Parity: 6 bytes (48 bits) of lightweight Forward Error Correction.

Unlike enterprise Ethernet (which utilizes heavy Reed-Solomon RS(544, 514) codes that add over 100 ns of algorithmic decode latency), PCIe Gen 6 selected a lightweight single-symbol correctable code that decodes in less than 2 nanoseconds. This near-zero latency penalty is essential to preserving CPU cache coherency protocols (such as CXL). If an error pattern exceeds the FEC's correction threshold, the 8-byte CRC instantly catches the corrupted FLIT and commands a fast hardware-level replay from the link partner's buffer.

Transmitter linearity and SNDR. In NRZ links, transmitter quality was measured simply by rise time and total voltage swing. In PAM4, non-linear driver compression between the four levels (L0, L1, L2, L3) degrades margin faster than dielectric loss. Gen 6 mandates strict linearity metrics:

  • Level Separation Mismatch Ratio (RLM): Measures whether the three eye heights are evenly spaced. Standards require RLM ≥ 0.95; uneven spacing compresses the middle or upper eye, making it disproportionately vulnerable to noise.
  • Signal-to-Noise-and-Distortion Ratio (SNDR): Quantifies total transmitted signal power against the sum of driver non-linearity, harmonic distortion, and random noise. Gen 6 requires an SNDR of at least 31.5 to 32 dB measured through a reference compliance channel.

In the real world

Gen 6 changes the character of signal integrity work on PCIe more than any previous generation did. NRZ debugging was mostly about loss and reflections, which are fixed with geometry and materials. PAM4 debugging is mostly about noise, linearity and error statistics.

The practical consequence is that the first instinct has to change. On a marginal NRZ link the question was usually "how do I get less loss?". On a marginal Gen 6 link it is more often "what is adding noise, and does it arrive in bursts?".

Related

Sources

Rows marked with a claim id are tracked in the claim ledger, which records what each source can and cannot establish.