DisplayPort 2.1: UHBR Rates, Cable Loss and Link Training

At a glance

What rates does DisplayPort run at?

Seven, per lane: RBR 1.62, HBR 2.7, HBR2 5.4 and HBR3 8.1 Gb/s with 8b/10b coding, and UHBR10, UHBR13.5 and UHBR20 at 10, 13.5 and 20 Gb/s with 128b/132b coding (C-208). A link runs one rate on all its lanes, one, two or four of them.

How much video does UHBR20 carry?

Four lanes at 20 Gb/s are 80 Gb/s on the wire. 128b/132b coding sends 128 data bits in every 132, so the coded payload is 4 × 20 × 128/132 = 77.58 Gb/s; VESA quotes a maximum payload of 77.37 Gb/s, slightly lower again for overhead inside the specification (C-204). HBR3 on four lanes carries 25.92 Gb/s after 8b/10b, so UHBR20 is three times as much.

Why do UHBR20 cables have to be short?

Because UHBR20’s Nyquist frequency is 10 GHz, and a cable loses more at 10 GHz than at HBR3’s 4.05 GHz: skin effect squeezes the current into a thinner and thinner layer of each wire as the frequency rises. VESA describes passive DP80 cables as limiting UHBR20 to about a metre, and its DP80LL active cables as reaching three (C-210).

What happens when the link cannot run at the top rate?

It runs at a lower one. During link training the source tries the highest rate both ends support, raising its drive strength over a few attempts; if the sink still cannot recover the clock, the source drops to the next rate down and tries again, until it succeeds or fails at the lowest (C-206). The picture still appears, but the payload, and with it the resolution or refresh rate on offer, falls.

What is an LTTPR?

A link-training tunable PHY repeater: a retimer that DisplayPort’s training knows about. It recovers the data and sends it again cleanly, so the path on each side of it is a link with a full loss budget of its own.

Can DisplayPort run over USB-C?

Yes, in DisplayPort Alt Mode. With all four high-speed lanes of a USB-C cable given to DisplayPort it carries up to 80 Gb/s; sharing the cable with SuperSpeed USB data leaves two lanes and up to 40 Gb/s (C-211).

A link with no clock wire

A DisplayPort link has three parts: up to four main-link lanes, each a 100 Ω differential pair (C-206); a slow auxiliary channel the two ends talk over; and a hot-plug detect line, which the sink raises to say it is there. There is no clock lane. The sink recovers each lane’s clock from the edges in the data, as a PCIe or USB receiver does (C-206).

That makes DisplayPort a SerDes link like any other, with one difference that shapes everything on this page: the rate is not fixed. PCIe trains down too, but a slot that comes up a generation low is a fault someone will chase; a DisplayPort link that cannot run UHBR20 settles for UHBR13.5 as a normal outcome, and the monitor offers fewer modes. Signal integrity on DisplayPort is less often “does it work” than “which rate does it reach”.

One budget for each rate, at its own Nyquist

Each rate’s loss is judged at its Nyquist frequency, half the bit rate, where a non-return-to-zero signal puts its fastest alternation. A path has one loss curve, but every rate reads it at a different point:

The UHBR budgets are die to die, from the source’s silicon to the sink’s, as a PHY vendor summarises the specification (C-205). HBR3’s is the low end of the 22 to 24 dB stress channel a DisplayPort 1.4 sink is calibrated against in compliance testing (C-207). That is a channel for testing a sink, not a die-to-die allowance: a sink has to cope with at least that much, so the panel’s HBR3 verdicts err on the cautious side. No public figure was found for the three slower rates, so the panel gives them HBR3’s, and says so; at their Nyquist frequencies the path loses so much less that they are never the rate that decides anything.

Notice that the budgets are not in order. UHBR13.5 is allowed less than UHBR10 or UHBR20. These are one vendor’s summary of the specification, and the page cannot tell you why UHBR13.5’s is the lowest; the panel uses them as published. That is one reason it checks each rate against its own budget rather than assuming that a path which fails one rate fails every rate above it.

Before you use the panel below, predict. A 1 m cable trains at UHBR20 with about 6 dB to spare. Triple the cable to 3 m. Does the link lose one rate, two, or fall all the way to HBR3? Then put a retimer beside the source’s connector: which rate does it get back?

The 3 m cable costs one rate: at 10 GHz the path loses about 26 dB against UHBR20’s 22.5, and at UHBR13.5’s 6.75 GHz it just fits 21 dB, with under a decibel to spare. The payload drops by a third, from 77.6 to 52.4 Gb/s. A retimer beside the source’s connector takes the source board out of the cable’s segment, and UHBR20 fits again by a fifth of a decibel. Put the retimer by the sink instead and it does not: the cable and the source board are still one segment, and that segment is the one that fails.

Where the decibels go

The panel builds the path from seven pieces, as an engineer would budget it. Three of them are physics you can change, the two board traces and the cable; the other four, two packages and two connectors, are allowances.

• Board traces. Dielectric and conductor loss of a 5 mil, 50 Ω trace (one side of the 100 Ω pair) on the chosen laminate, from the manufacturer’s published Dk and Df at each frequency, the same arithmetic as the loss budget calculator. At 10 GHz an inch of FR-4 loses about 1.7 dB and an inch of MEGTRON 4 about 0.96 dB.
• The cable. Each pair is two round copper wires of the chosen gauge, at 100 Ω. Its loss is worked out from the wire’s diameter: skin-effect resistance, the proximity effect of two wires side by side, and a little loss in the insulation. A bare pair is the floor, since a real cable also has a shield and a drain wire, so the conductor loss is scaled by one factor, about 1.38, which makes 30 AWG twinax lose what a worked example contributed to IEEE 802.3dj says it does at 53 GHz (C-118). The result is about 5.0 dB a metre at 10 GHz for 30 AWG and 7.7 for 34 AWG.
• Packages and connectors. 1.5 dB per package and 0.7 dB per mated connector at 10 GHz, scaled with frequency. These are illustrative: no public source gives them for DisplayPort, and they are labelled so in the panel’s model contract.

The cable is where the length lives, and the gauge is where the cable’s loss lives. Skin-effect resistance goes as one over the wire’s diameter, so the 34 AWG wire of a thin, flexible cable, about 0.16 mm across, loses half as much again as 30 AWG over the same length. Making a UHBR20 cable both thin and long is the hard part, which is why VESA certifies cables by the rate they carry.

Training: highest first, then down

Texas Instruments’ application note on DisplayPort 1.4 link training lays out the sequence (C-206). When the sink raises hot-plug detect, the source reads the sink’s capabilities over the auxiliary channel: its lane count, its rates, the drive levels it accepts. Clock recovery comes next. The source sends a simple training pattern on every lane at the highest rate the sink supports, at its lowest voltage swing and pre-emphasis, and after each interval asks the sink whether every lane has recovered a clock. Each “no” raises the drive a step. After five attempts at one rate the source gives up on it, drops to the next rate down, and starts again from the gentlest drive.

Once the clock is recovered, channel equalisation tunes the sink’s receiver on a richer pattern, and the sink reports symbol lock and lane alignment; then video starts. If the clock never recovers, even at the lowest rate with the strongest drive, training fails and the screen stays dark (C-206).

The panel’s Train button walks that ladder. It does not model the drive steps; it asks the question each rung of the ladder settles, whether the path fits the rate’s budget, and stops at the first yes. The UHBR rates use 128b/132b and a different training sequence in its details, which the public note does not cover; the step-down pattern is the same.

Retimers split the budget

A linear redriver boosts the high frequencies and passes the noise and distortion along with them; the budget it helps with is still one budget. A retimer recovers the bits and transmits them afresh, so the path on each side of it is a separate link with the whole budget to itself. DisplayPort’s name for a retimer that takes part in training is a link-training tunable PHY repeater, or LTTPR.

The panel’s two positions show the catch. A retimer helps only the segment it shortens. Beside the source’s connector it removes the source board from the long segment; by the sink it removes only the sink board, and the cable, still the largest term, stays with the source board on the far side. A retimer also brings a package of its own into each segment, so it never gains quite the loss it removes.

Cables: DP40, DP80 and DP80LL

VESA certifies UHBR cables by the rate they carry on four lanes. A DP40 cable supports UHBR10, 40 Gb/s on the wire; a DP80 cable supports UHBR20, 80 Gb/s, and UHBR13.5 too (C-209). In January 2025 VESA added DP80LL, a low-loss active cable that carries UHBR20 over up to three metres, against about one metre for a passive DP80 cable (C-210). What an active cable contains is the maker’s choice and the release does not say.

A certified cable is a guarantee about the cable, not about the link. Its share of the budget assumes boards and packages that leave it room; a long trace on FR-4 at either end can use up the margin the certification was counting on. Take the “Desk” preset, set the laminate to FR-4 and drag the source trace to 8 in: the same certified 1 m cable now trains at UHBR13.5, and at 10 in UHBR10.

DisplayPort over USB-C

In DisplayPort Alt Mode, a USB-C port hands its high-speed lanes to DisplayPort. All four give the full rate; a port that keeps two for SuperSpeed USB data gives DisplayPort the other two, up to 40 Gb/s (C-211). Full-featured passive USB-C cables already carry the UHBR rates (C-209). On a laptop the limit is often not loss at all: two lanes at HBR3 carry 12.96 Gb/s, enough for 4K at 10 bits a colour only up to about 52 frames a second before blanking. The “Laptop USB-C” preset trains with nearly 8 dB to spare and still cannot drive a fast 4K monitor.

Why this decides how your board behaves

• The result of a marginal path is a lower rate, not a failure. It shows up as a missing refresh rate in a monitor’s menu, which nobody files as a signal-integrity bug.
• The cable is the customer’s. A source board has to leave room for any certified cable a customer plugs in, so its own share has to be met with the longest cable the product claims to support.
• Each rate is checked at its own frequency. Fixing loss at 10 GHz with a low-loss laminate helps UHBR20 most and HBR3 hardly at all.
• A budget is not an eye. Reflections at connectors, crosstalk between lanes and jitter all take margin this panel does not count; it answers the first question, not the last.

What to do about it

• Budget the source board for the longest cable the product supports at the top rate, and check every rate at its own Nyquist.
• Keep UHBR20 traces short and on a lower-loss laminate; an inch of FR-4 at 10 GHz costs nearly twice what an inch of MEGTRON 4 does.
• If the path will not fit, place a retimer so that it splits the largest segment, usually next to the connector on the side with the long trace.
• Route the main link as 100 Ω ± 10% pairs (C-206), and, as for any SerDes lane, match the two lines of each pair in length and leave no via stubs.
• When a link trains low, read the training over the auxiliary channel: the rate and drive levels it settled on tell you which rung failed and how hard it tried (C-206).

Go deeper — the payload arithmetic, the cable model, and what is not sourced here

The payload arithmetic. Payload is lanes × rate × coding efficiency. 8b/10b sends 8 data bits in 10, 80%; 128b/132b sends 128 in 132, 97.0% (C-208). HBR3 on four lanes: 4 × 8.1 × 0.8 = 25.92 Gb/s, VESA’s own figure for DisplayPort 1.4a (C-204). UHBR20: 4 × 20 × 128/132 = 77.58 Gb/s, while VESA quotes 77.37 Gb/s, or 19.34 Gb/s a lane (C-204, C-211). The specification has overhead beyond the line coding that the public releases do not itemise, so this page computes the coding ratio and reports VESA’s number beside it rather than inventing a breakdown.

The video arithmetic. The “4K 10-bit” readout divides the payload by 3840 × 2160 pixels × 30 bits: 311 frames a second at UHBR20 and 104 at four lanes of HBR3. It counts active pixels only. Real timings add blanking, which lowers these, and Display Stream Compression, which the specification supports (C-204), raises them by its compression ratio. It is arithmetic, not signal integrity, and is there to show what a step down the ladder costs.

The cable model. For two round wires of diameter d, centres D apart, in a uniform insulation of relative permittivity ε_r and nothing else nearby, the differential impedance is exactly

Z = (120/√ε_r) · arccosh(D/d)

so 100 Ω fixes D/d. A real twinax pair, with its foil, shield and drain wire, comes close to this but not exactly. At high frequency the current in each wire crowds towards the other, and the resistance of the pair per metre is

R′ = (2R_s / πd) · (D/d) / √((D/d)² − 1)

with R_s the surface resistance of copper. The loss is R′/2Z nepers a metre from the copper plus πf√ε_r·tanδ/c from the insulation, here ε_r = 2.1 and tanδ = 0.0003, an illustrative polyolefin. The conductor term is then multiplied by the single factor that reproduces C-118’s 30 AWG twinax, 2.2 dB in 6.8 in at 53.125 GHz. That factor carries everything a bare pair leaves out (shield, drain, plating, the shape of real conductors) as one number, and the same number is used for every gauge and length.

What is not sourced here. VESA’s DisplayPort specification and compliance test specification are for members. The rates, coding and cable classes come from VESA’s public releases and an IP vendor’s glossary; the UHBR budgets from a PHY vendor’s summary; HBR3’s from a test-equipment vendor’s method of implementation; the training sequence from a TI application note written to DisplayPort 1.4a. The slower rates’ budgets, the package and connector allowances and the cable’s insulation are assumptions, labelled where they are used, and each sourced figure is in the claim ledger with what it can and cannot establish.

In the real world

DisplayPort links run from graphics cards to monitors, from laptops through USB-C docks, and inside laptops as embedded DisplayPort to the panel. The ones that reach UHBR20 are short, or retimed, or both; the rest train lower and nobody notices unless the monitor’s fastest mode goes missing.

The engineering is the arithmetic this page has drawn: a budget per rate at its own frequency, a cable the customer chooses, and a ladder that settles wherever the path lets it. Getting the top rate is a matter of leaving the cable the room its certification assumed.

Related

• HDMI 2.1: FRL, TMDS and Whether the Link Trains
• USB 3.x
• PCIe 4.0 and 5.0
• Connectors and cables
• Loss mechanisms
• Channel budgeting