HDMI 2.1: FRL, TMDS and Whether the Link Trains

By Geetansh Arora — Principal SI/PI Engineer1 Nov 202610 min

HDMI 2.1 added Fixed Rate Link (FRL): up to four lanes at up to 12 Gb/s each with the clock embedded in the data, coded 16b/18b, for 48 Gb/s on the wire and about 42.7 Gb/s of payload. The old TMDS clock lane becomes the fourth data lane (C-212, C-214). Which FRL rate a link reaches is a loss question at each rate’s Nyquist frequency, and if FRL training fails, the link falls back to TMDS and runs as HDMI 2.0 (C-212).

At a glance

What is the difference between TMDS and FRL?

TMDS, used up to HDMI 2.0, sends data on three lanes and a clock on a fourth; the receiver samples the data with that forwarded clock. FRL, added in HDMI 2.1, embeds the clock in the data, recovers it at the receiver, and turns the clock lane into a fourth data lane (C-212, C-213).

What rates does FRL run at?

Six combinations: 3 or 6 Gb/s on three lanes, and 6, 8, 10 or 12 Gb/s on four (C-212, C-214). TMDS ran at up to 3.4 Gb/s a lane in HDMI 1.4b and 6 Gb/s in HDMI 2.0, 10.2 and 18 Gb/s across three lanes (C-212).

How much video does 48 Gb/s carry?

FRL’s 16b/18b coding sends 16 data bits in every 18, so four lanes at 12 Gb/s carry 48 × 16/18 = 42.67 Gb/s. TMDS used 8b/10b, 8 bits in 10 (C-212). The two efficiencies stand in the ratio (16/18)/(8/10) = 10/9: FRL carries a ninth more data for each bit on the wire.

What happens when a link cannot run FRL at 12G?

The source and sink go through FRL link training, and the rate can be changed and trained again. If FRL training fails or times out, both ends drop to legacy TMDS and run in HDMI 1.4b or 2.0 mode (C-212). The picture appears, at whatever that rate carries.

Which cable do I need for 48 Gb/s?

One certified as an Ultra High Speed HDMI Cable, the class HDMI 2.1 introduced for configurations up to 48 Gb/s. Its certification is mandatory for the label and includes an EMI test (C-215).

Four lanes, and where the clock went

An HDMI connector has four high-speed pairs. Under TMDS three carry data and one carries a clock at a tenth of the lane rate, or a fortieth at HDMI 2.0’s highest rates (C-212). FRL keeps the same connector and the same pairs and reassigns them: the three data pairs become FRL lanes 0 to 2 and the clock pair becomes lane 3, unused in the three-lane modes (C-214). Each lane now carries its own timing in its edges, as DisplayPort and PCIe lanes do.

Two things follow for the board. The pair that used to carry a modest clock now carries 12 Gb/s data, so it needs the same care as the others: an FPGA vendor’s guide routes all four at 90 to 100 Ω and uses 95 Ω connectors and cables (C-213). And a receiver that supports both modes has to take that pair to a clock input for TMDS and to a data input for FRL; the same guide uses a fan-out buffer at the receiver to do it (C-213).

A budget at each rate’s Nyquist

As on DisplayPort, each rate’s loss is judged at half its bit rate: 6 GHz for FRL 12G, 5 GHz for 10G, 4 for 8G, 3 for the 6 Gb/s modes and 1.5 for 3G. The one public figure for the loss an HDMI 2.1 receiver has to handle is the worst-case cable model an FPGA vendor tests its sink through at FRL 12G: a channel of 20.18 dB (C-213). The panel uses 20 dB at 6 GHz as FRL 12G’s budget and, with no public figure for the others, gives every HDMI rate the same 20 dB, labelled so.

That makes the panel cautious. A sink is tested with the worst-case cable at its connector, so its own board and package come on top of the 20 dB, where the panel counts them inside it. Intel’s guide shows how tight the real path is: it allows the cable up to 16 dB at 12 Gb/s and puts redrivers on the boards to cover the rest (C-213). Read the panel’s verdicts as a few decibels on the safe side.

Before you use the panel below, predict. A 2 m cable trains at FRL 12G with about 3 dB to spare. Double it to 4 m: does the link lose one rate or two? Then add a retimer by the television’s connector.

Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.

Will it train? numerical trains at — payload — margin — 4K 10-bit up to —

Insertion loss · each segment, with every rate’s budget at its Nyquist

path, or before the retimerafter the retimereach rate’s budget (the slowest unnamed)

Link training · FRL from the top, then TMDS

The 4 m cable costs two rates. At 6 GHz the path loses about 23 dB, and at 5 GHz still more than 20, so FRL 12G and 10G both fail and the link settles at FRL 8G: 28.44 Gb/s, two thirds of the top rate’s payload. Hold that verdict loosely: FRL 10G misses by only about 0.2 dB, against a budget the panel assumes, and the cable lengths are typical thin-cable examples, not certification limits. A certified cable is held to a loss mask, not a length, and Intel’s guide lets one lose up to 16 dB at 12 Gb/s (C-213). A retimer by the television’s connector takes its 4 in board out of the long segment and FRL 12G fits again. Unlike the DisplayPort example, this one helps more by the sink, because here the sink has the longer trace.

Where the decibels go

The panel builds the path the same way as the DisplayPort panel, from the same model. The board traces are 5 mil, 50 Ω traces on the chosen laminate, from the laminate’s published Dk and Df: FR-4 loses about 1.09 dB an inch at 6 GHz. The cable is a two-wire line of the chosen gauge at 100 Ω, with skin effect and proximity effect worked out from the wire’s diameter and one construction factor fitted to a published twinax figure (C-118): 28 AWG loses about 3.1 dB a metre at 6 GHz and 32 AWG about 4.7. Packages and connectors are illustrative allowances, labelled so.

For the 2 m television link at 6 GHz that comes to about 6 dB of cable, 3.3 and 4.4 dB of source and sink board, a decibel for each package and half a decibel for each connector: about 17 dB against 20. The cable is the largest single term, and the boards together are larger still. That is the usual shape of an HDMI path, and why a certified cable is necessary but not sufficient.

Training FRL, and falling back to TMDS

A source first reads the sink’s EDID, which says whether it supports FRL and the highest FRL rate it accepts, on a scale from 1 (3G on three lanes) to 6 (12G on four). If it does, the source sets an FRL rate and a transmitter equalisation level and sends training patterns, and the sink asks for the patterns it needs on each lane over the status and control channel. When every lane is satisfied, FRL transmission starts. A separate state exists for changing the FRL rate and training again. If training fails or times out, both ends go to legacy TMDS and run as HDMI 1.4b or 2.0 (C-212).

The panel’s ladder tries the FRL rates from the top, then TMDS. The specification’s order for retrying a lower FRL rate before giving up on FRL is not in the public material, so treat the ladder as the shape of the decision rather than the exact sequence. Notice what the loss alone does: TMDS at 6 Gb/s has the same Nyquist frequency as FRL at 6G, so a path that fails FRL 6G on loss fails TMDS 6G too, and FRL 3G, at half the frequency, fits first. When a real link lands in TMDS, the cause is usually a sink without FRL, or a training failure that is not plain loss: a reflection, a marginal lane, a cable that is not what its label says.

Why this decides how your board behaves

The fourth pair is a data lane now. A clock pair routed with a clock’s tolerance will be the lane that fails FRL training.
The result of a marginal path is a lower rate. It shows up as a television that will not offer 4K at 120 Hz, not as a dark screen.
The cable is the customer’s. A source and sink have to leave the cable the room its certification assumes, with the longest cable the product claims to support.
A budget is not an eye. Reflections, crosstalk and jitter take margin this panel does not count.

What to do about it

Route all four pairs to the same rules, at 90 to 100 Ω with matched lengths (C-213).
Keep both boards’ traces short; at 6 GHz an inch of FR-4 costs about a decibel, which is a metre of thin cable’s worth every four inches.
Plan for a redriver or retimer where a long trace and a long cable meet. The FPGA vendor’s guide puts a redriver on its board, at the receiver, where an integrated fan-out buffer also splits FRL lane 3 off to the TMDS clock input, and notes that longer traces need more equalisation (C-213). A redriver is linear: it restores the high frequencies but does not split the path into two budgets the way the panel’s retimer does.
Support TMDS properly on a dual-mode receiver: the pair that is FRL lane 3 has to reach a clock input too (C-213).
Test with certified Ultra High Speed cables at the longest length you claim (C-215).

Go deeper — the payload arithmetic, why the clock lane mattered, and what is not sourced here

The payload arithmetic. Payload is data lanes × rate × coding. FRL 12G on four lanes: 4 × 12 × 16/18 = 42.67 Gb/s, which carries 4K at 10 bits a colour up to 171 frames a second before blanking. FRL 6G on four lanes: 21.33 Gb/s. TMDS 6G, HDMI 2.0’s top rate: 3 × 6 × 8/10 = 14.4 Gb/s, because the fourth pair carries the clock and no data. The step from HDMI 2.0 to 2.1 is therefore a third more data lanes, twice the lane rate and a ninth better coding: 42.67 Gb/s against 14.4, close to three times the payload.

Why the clock lane mattered. A forwarded clock is the simplest timing there is, and it costs a lane: under TMDS a quarter of the pairs carried no data. Recovering the clock from the data frees that lane and removes the skew between clock and data that a forwarded clock has to be matched against; the price is a clock-recovery circuit in every lane and the link training that sets it up.

What is not sourced here. The HDMI 2.1 specification is available to HDMI adopters, and its compliance test specification likewise. The rates, lanes, coding and training states come from a test-equipment vendor’s public reading of the specification and a redriver vendor’s application note; the 20 dB from an FPGA vendor’s design guide; the cable class from the licensing body. The budgets of the rates below FRL 12G, the package and connector allowances and the cable’s insulation are assumptions, labelled where they are used, and each sourced figure is in the claim ledger.

In the real world

HDMI 2.1 links run from consoles, set-top boxes and graphics cards to televisions and monitors, often through a receiver or a soundbar on the way. Every one of those boxes is a source board and a sink board, and every cable between them is the customer’s choice.

The engineering is the same arithmetic as on DisplayPort, with one difference worth remembering: the fourth pair changed jobs. A board laid out for HDMI 2.0, with a clock pair that never had to carry data, is the board most likely to train below the rate its silicon supports.

Sources

Rows marked with a claim id are tracked in the claim ledger, which records what each source can and cannot establish.