USB 3.2 Gen 1 vs Gen 2 vs Gen 2x2: Loss Budget, SSC and Compliance

At a glance

USB 3.0 vs 3.1 vs 3.2: what is the difference?

Mostly names. USB 3.0 (2008) defined 5 Gbps signalling; USB 3.1 (2013) added 10 Gbps and called the two rates Gen 1 and Gen 2; USB 3.2 (2017) absorbed both and added two-lane operation over Type-C, Gen 1x2 at 10 Gbps and Gen 2x2 at 20 Gbps (C-143, C-144, C-146). A “USB 3.0” port and a “USB 3.2 Gen 1” port are electrically the same 5 Gbps link. The naming table lines them up.

How fast is USB 3.2 Gen 2x2 really?

After line coding, one Gen 1 lane carries 500 MB/s and one Gen 2 lane about 1.2 GB/s; two lanes double that, to 1 GB/s and about 2.4 GB/s for Gen 2x2. Framing, flow control and protocol overhead then bring an application down to 450 MB/s or less per Gen 1 lane and about 1.1 GB/s or less per Gen 2 lane (C-145). Gen is the rate per lane; the “x2” is the lane count.

What is the USB 3.2 Gen 2 loss budget?

23 dB at 5 GHz, from a host or device transmitter to the receiver at the far end (C-152). A passive Type-C cable may take 6 dB of that (C-153), which leaves 8.5 dB for each end: the same 8.5 dB the Type-C specification gives a transmitter in a cable plug driving into a controller (C-152). The budget section walks through it.

How long can a USB-C cable be for 10 Gbps?

The Type-C specification lists the practical length of a passive Gen 2 cable as up to 1 m, and a Gen 1 cable as up to 2 m (C-153). Those lengths are informative; what a cable must actually meet is a loss limit, no worse than −6 dB at 5 GHz for Gen 2 and −7 dB at 2.5 GHz for Gen 1. With the specification’s own raw-cable examples, 6 dB at 5 GHz is just under 1 m of 34 AWG coax and about 1.9 m of 28 AWG, before the plugs take their share (C-153, C-154).

Is spread-spectrum clocking required for USB 3.2?

Yes, on every port. The data rate is pulled down by between 4000 and 5000 ppm at its deepest and back again, 30 to 33 thousand times a second; the shape of the sweep is up to the vendor (C-15). The receiver’s clock recovery has to follow it, so a simulation or a bench test with a fixed clock leaves out a term the specification assumes is there.

What equalization does USB 3.2 use?

A Gen 1 transmitter applies 3.0 to 4.0 dB of de-emphasis; a Gen 2 transmitter has a three-tap filter with 1.2 to 3.2 dB of preshoot and 2.1 to 7.0 dB of de-emphasis (C-147). For compliance the receiver is modelled as a continuous-time linear equaliser (CTLE) at Gen 1, and as a CTLE plus a one-tap decision feedback equaliser (DFE) at Gen 2. Real receivers may use anything, and train on a pattern sent during link-up (C-150).

Why does Gen 2x2 need a Type-C connector?

Because it needs two transmit pairs and two receive pairs, and only Type-C has them. Dual-lane operation is defined for Type-C only (C-146). The receptacle has two sets of SuperSpeed pins so the plug can go in either way up; one lane uses whichever set the orientation selects, and two lanes use both, with the CC pins deciding which is Lane 0 (C-155).

What impedance does USB 3.2 use?

Type-C cables and connectors are specified with S-parameters normalised to 85 Ω differential, and a mated connector should sit within 85 ± 9 Ω (C-154). The transmitter’s own DC differential impedance may be 72 to 120 Ω (C-147). The specifications do not fix your board’s trace impedance; they expect each silicon vendor to publish layout guidelines for its part (C-156), and those are where the number comes from.

Why USB is a channel you do not own

Most links on this site are a channel you can measure. A PCIe link lives entirely inside a product, and an LPDDR bus is a few centimetres of your own board: you can build it, characterise it and sign it off. A USB channel is your board, then a connector, then a cable of unknown length and quality made by someone you have never met, then a product you have never seen. At Gen 2 your share is 8.5 of the 23 dB, about 37%; the other 63% arrives with the user.

So the design target is different. It is not “make this channel good”, because you cannot. It is “leave as much margin as you can for the part you do not control”, and that idea drives every decision below. USB makes it workable by specifying the parts nobody owns: every cable must meet a loss limit, every transmitter must produce a defined eye at the end of a worst-case reference channel, and every receiver must tolerate a defined stressed signal.

USB 3.0, 3.1 and 3.2 names, decoded

The renaming caused more confusion than any electrical change. Each new specification absorbed the old one and renamed what was already there, so one 5 Gbps link has had three names.

For signal integrity the useful labels are the Gen number, which fixes the rate on each wire, and the lane count. A Gen 1x2 link and a Gen 2x1 link both carry 10 Gbps raw, but the first does it with 5 Gbps on each of two lanes and 8b/10b coding, so it delivers less to the application and puts half the frequency on each pair.

USB 3.2 Gen 1 vs Gen 2 vs Gen 2x2, side by side

USB 3.2 Gen 2 loss budget: where the 23 dB goes

The Type-C specification states the end-to-end figure directly: a host or device transmitter must drive 23 dB of loss at 5 GHz to the far side (C-152). It also says a transmitter sitting in a cable plug, right next to the port it drives, only has to cover 8.5 dB to the controller’s receiver. That 8.5 dB is one product’s share of the channel: package, board trace, any orientation switch or redriver, and the receptacle. Two of them plus the 6 dB a passive cable is allowed (C-153) make 8.5 + 6 + 8.5 = 23 dB.

Twenty-three decibels at 5 GHz means about 7% of the launched 5 GHz amplitude arrives. The low-frequency content survives much better, so the waveform at the far pin is smeared rather than small, and the USB 3.2 specification says plainly that for long cables and channels the eye at the receiver is closed until it is equalised (C-150). That is the expected state of a compliant link, not a fault.

The cable’s 6 dB is why its length is limited. The Type-C specification’s raw-cable examples put coaxial pairs at 6.1 dB/m at 5 GHz for 34 AWG and 3.1 dB/m for 28 AWG (C-154): just under 1 m and about 1.9 m of raw cable respectively, before the plugs and their transitions take a share. The practical lengths in the specification, up to 1 m for Gen 2 and up to 2 m for Gen 1, follow from that arithmetic (C-153).

Your 8.5 dB has to cover everything between the silicon and the receptacle. Treat it as an allowance to stay well inside rather than a target. Margin you leave on the board is margin available to a worse cable, and the silicon vendor’s layout guidelines, which the USB specification expects every part to have (C-156), are where the board share is turned into trace lengths and via rules.

Spread-spectrum clocking: what USB 3.2 requires

Every USB 3.2 port must spread its clock (C-15). The data rate is swept down from nominal and back at 30 to 33 kHz, and the deepest point must land between −4000 and −5000 ppm below nominal. Only down-spread is allowed: the sweep only ever slows the clock. The shape of the sweep is the vendor’s choice, but however it is shaped, its rate of change may not exceed 1250 ppm/µs.

Spreading the clock spreads the energy of each harmonic across a band of frequencies instead of concentrating it in one narrow line, which lowers the peak an emissions measurement sees. The cost lands on the receiver: its clock and data recovery (CDR) has to follow a clock that is always moving, so SSC tracking is a real part of the jitter budget, and the receiver test keeps SSC switched on throughout (C-151). A simulation of a USB link with a fixed clock leaves out a term the specification assumes is there.

How closely can it follow? The CDR here is a type-2 loop, which follows a steady frequency ramp with a constant lag: the ramp’s rate divided by the square of the loop’s natural frequency, taken in radians per second, ω_n = 2πf_n. On the 30 kHz triangle above, slewing at 300 ppm/µs, a loop with f_n = 1 MHz (ω_n = 2π × 10⁶ rad/s) lags by about 7.6 ps; on a profile that slews at the 1250 ppm/µs limit, by about 32 ps. Ten times the loop bandwidth is a hundred times less lag, which is why SSC sets a floor under the CDR bandwidth. Predict where a loop starts to lose a whole UI at Gen 2, then find it below.

USB 3.2 equalization: de-emphasis, preshoot and the reference receiver

With most of the loss outside your product, the link relies on equalisation at both ends, and the specification defines each end differently.

• Gen 1 transmitter: de-emphasis. Each bit after the first in a run is sent at a lower level, 3.0 to 4.0 dB below a transition bit, nominally 3.5 dB (C-147). That pre-distorts the waveform the opposite way to the channel’s low-pass loss.
• Gen 2 transmitter: three taps. A three-tap filter adds preshoot, 1.2 to 3.2 dB, which boosts the bit before a transition, to the de-emphasis, 2.1 to 7.0 dB (C-147). The definitions match PCIe’s: preshoot is 20·log(Vc/Vb), de-emphasis 20·log(Vb/Va), and the three tap weights sum to one. The deeper section works one setting through.
• Reference receiver. Compliance models the receiver as a CTLE at Gen 1, and as a first-order CTLE followed by a one-tap DFE limited to 0 to 50 mV at Gen 2 (C-150). These are yardsticks for measuring a transmitter, not a design the receiver must copy; real receivers are implementation-specific.
• Training. At link-up the transmitter sends a training pattern, TSEQ, so the receiver can adapt: 65,536 repetitions at Gen 1 and about 8 ms at Gen 2 (C-150). The USB 3.2 specification defines no exchange like PCIe’s link equalization, in which a receiver asks the far transmitter for different settings; the transmitter’s setting is chosen by its designer, and the receiver adapts to what arrives.

Type-C orientation and dual-lane Gen 2x2

A Type-C plug goes in either way up, so the receptacle carries two sets of SuperSpeed transmit and receive pins. The CC pins tell the host which way the plug went in. That fixes the lane ordering and, for two-lane operation, which pair is the Configuration Lane, and it lets a host or device route the signals if it needs to (C-155). A single-lane design needs something to pick the right set: a switch, a redriver with a switch built in, or a controller that does it on chip. Whatever does it sits in the signal path and spends part of your 8.5 dB.

Gen 2x2 uses both sets at once, which is why it exists only on Type-C (C-146). The two lanes may arrive up to 6400 ps apart, 64 unit intervals at Gen 2, and the receiver realigns them, so the lanes need not be length-matched to each other the way the two wires of a pair must be. When a two-lane link cannot hold up, it steps down in a defined order.

How USB 3.2 is signed off: the compliance eye and jitter tolerance

USB compliance is a defined set of measurements rather than an in-house simulation flow, and it tests each part of the channel against a worst-case version of the others.

• Transmitter. Measured at TP4, at the end of a reference channel and a compliant cable, after the reference receiver equaliser has been applied. The eye must be at least 100 mV high with at most 0.66 UI of total jitter at Gen 1, and at least 70 mV with at most 0.671 UI at Gen 2, extrapolated from a million unit intervals to a bit error ratio of 10⁻¹² (C-149). The specification notes that without the reference equaliser the eye there may be closed.
• Receiver. A pattern with calibrated random and sinusoidal jitter goes through the compliance reference channel, with SSC present the whole time, and the receiver loops the data back to be checked. Above the corner frequency (4.9 MHz at Gen 1, 7.5 MHz at Gen 2) it must tolerate 0.2 and 0.17 UI of sinusoidal jitter; below it, much more, because the CDR is expected to track slow jitter (C-151).
• Cable. Every cable assembly must meet a fitted loss at each Nyquist frequency, limits on multiple reflections, crosstalk and return loss, and a mode-conversion limit (C-153).

Because the reference channels stand in for the worst real ones, passing your own simulation is evidence, not the result. The result is the compliance measurement, and the silicon vendor’s layout guidelines are written to make it pass (C-156).

Why this decides how your board behaves

• Your share of the loss should be small on purpose. Using all 8.5 dB because the budget allows it leaves nothing for a poor cable or a lossy device at the far end.
• The connector launch is the part you own and the part most likely to fail. A Type-C footprint is a dense, fine-pitch structure exactly where the signal leaves your board, and its electrical footprint is something you design.
• Compliance is the mechanism, not a formality. It is the only guarantee about the far end, so its test conditions are the real contract.
• The common-mode path leaves the product. A cable is an antenna attached to your board, which makes mode conversion an emissions problem as well as a signal one.

What to do about it

Spend less than your allocation. Shorter routes, fewer vias and a better launch than the budget strictly requires. The margin you keep is available to a cable or a product you never tested with.

Design the connector footprint deliberately. Ground provision, antipad geometry, and via stubs on through-hole pins. It is the highest-leverage part of the channel you own. See connectors and cables.

Count the orientation switch in the budget. If one lane’s worth of pins is chosen by a switch or redriver, its loss and its two sets of transitions come out of your 8.5 dB.

Treat shield termination as a return-path decision. A 360° bond gives common-mode current a defined low-inductance path; a pigtail does not, and above the frequency where its inductance dominates, the shield stops working.

Keep each pair symmetric right up to the connector. Mode conversion on your board becomes common-mode current on someone else’s cable, and that is what fails an emissions scan. The cable itself is held to −20 dB of mode conversion at Gen 2 (C-153); your board deserves the same care.

Go deeper — the Gen 2 tap algebra, the SSC arithmetic, and where common mode goes

One Gen 2 setting, worked through. The receiver jitter-tolerance stimulus uses 2.2 dB of preshoot and −3.1 dB of de-emphasis (C-151). With the taps scaled so their magnitudes sum to one, a lone bit reaches the full swing Vd = 1, and the three ratios give two equations in the two outer taps. Their solution is c₋₁ = −0.084 and c₊₁ = −0.125, so the main tap is c₀ = 0.791; the steady level of a long run is Vb = 0.582, and the boost is 20·log(1/0.582) = 4.7 dB. These are the same values an earlier revision of the specification printed as informative for its single nominal setting, before an engineering change notice replaced it with today’s range (C-147). The algebra is the one on the PCIe preset page.

How far SSC moves the data. Take a 30 kHz triangle with 5000 ppm depth. Its frequency swings ±2500 ppm about the average, and the phase is the running sum of that offset: over each half-cycle of 16.7 µs the data gains or loses ½ × 2500 ppm × 16.7 µs ≈ 21 ns against an average-rate clock. That is about 104 unit intervals at Gen 1 and 208 at Gen 2. The sweep is slow, though: the triangle slews at 300 ppm/µs, a quarter of the 1250 ppm/µs limit (C-15), so a CDR with enough bandwidth to follow a 33 kHz modulation tracks it with little residual error. The jitter tolerance curve encodes the same idea: it asks for large jitter tolerance at low frequencies and only 0.17 UI at Gen 2 above 7.5 MHz (C-151).

AC coupling. Every USB 3.2 transmitter is AC coupled, with 75 to 265 nF in each line, placed with the transmitter or in the cable (C-148). Two products designed independently therefore need not agree on a common-mode voltage. It has two consequences worth knowing. Low-frequency content is blocked, which is why the line coding must guarantee enough transitions. And the capacitors are a discontinuity: a real part has a pad and package inductance, and at the top of the band it is not the short circuit the schematic implies.

Common mode is the part that leaves the product. Differential current on a well-matched pair largely cancels in the far field. Common-mode current does not: it flows out along the cable, using the shield and whatever else it can find as a return, and radiates from a structure the size of the cable. The chain is worth stating because it crosses topics usually kept apart: asymmetry on your board → mode conversion → common-mode current → an emissions failure on a cable you did not design. The cable is held to SCD21 ≤ −20 dB at Gen 2 and −17 dB at Gen 1 for exactly this reason (C-153). See differential signalling for the conversion mechanism and SCD21 as the measurement that predicts it.

In the real world

USB is often treated as a solved problem, and its surprises tend to come late because they come from outside the product: a cable, a hub, a device, or an emissions scan with something plugged in that was not there during development. The specification anticipates this by setting limits on every part that nobody owns, which is what lets a well-made board work with products it has never met.

The defence is margin rather than analysis. You cannot simulate a channel you have never seen, so the useful move is to make your third of it, the 8.5 dB between your silicon and your receptacle, as good as you reasonably can, and to leave the rest of the budget for whatever the user plugs in.

Where the numbers come from

The electrical limits on this page were read from the USB 3.2 specification, Revision 1.1, and the USB Type-C Cable and Connector Specification, Release 2.5, both free to download from USB-IF. Clause and table numbers are in the claim ledger. The ledger marks normative rows as scoped rather than verified: they were checked against the document, and a sign-off should still be read from the revision you are designing to. The rates, unit intervals, cable reaches and SSC arithmetic are derived here and checked on every build.

Related

• Differential Signaling: Common Mode and Mode Conversion
• Transmitter Compliance Masks and Receiver Eye Masks
• High-Speed Connectors and Cables
• SerDes Equalization: CTLE, FFE, DFE and CDR
• Jitter Components: RJ, DJ, DCD, PJ, and TJ
• PCIe 4.0 vs 5.0: Loss Budget, Tx Presets, Link Equalization