MIPI D-PHY vs C-PHY: Forwarded Clock, Trios and Three-Level Signalling

By Geetansh Arora — Principal SI/PI Engineer1 Nov 202610 min

D-PHY and C-PHY are MIPI’s two physical layers for cameras and displays. D-PHY sends a clock on its own lane beside differential data lanes, and drops to slow single-ended signalling between bursts. C-PHY drops the clock lane altogether: it drives three wires at once, a trio, at three voltage levels, and guarantees that the wires change state on every symbol, so the receiver finds the clock in the data. The same SoC pins can often do both (C-200).

At a glance

What is the difference between D-PHY and C-PHY?

D-PHY is a differential pair per data lane plus one more pair for the clock; the transmitter forwards its clock and the receiver samples the data with it (C-202). C-PHY replaces pairs with trios of three wires, encodes data in the change from one of six wire states to another, and needs no clock lane, because every symbol is a change (C-199, C-202). D-PHY v3.5 added an optional embedded-clock mode of its own, which frees the clock lane for data (C-201).

How fast are D-PHY and C-PHY?

MIPI gives D-PHY v3.0 9 Gb/s a lane over its standard channel and 11 Gb/s over its short channel (C-201). C-PHY runs up to 6 gigasymbols a second in its 6-wirestate mode, about 13.7 Gb/s a trio, so three trios on nine wires carry about 41 Gb/s; the 18-wirestate mode that C-PHY v3.0 added runs at up to 5 Gsps for 17.8 Gb/s a trio (C-199).

Why does C-PHY carry about 2.28 bits per symbol?

From any wire state there are five others to move to, so one symbol could carry log₂5, about 2.32 bits. C-PHY packs 16 bits into 7 symbols, because 2¹⁶ = 65,536 fits inside 5⁷ = 78,125: 2.29 bits a symbol (16/7 = 2.2857), which MIPI gives, cut short rather than rounded, as approximately 2.28 (C-199, C-202).

What are LP-11, LP-01 and LP-00?

They are D-PHY’s low-power line states, named by the levels on the two wires of a lane. A lane rests in LP-11, both wires high, and enters high-speed mode by stepping through LP-01 and LP-00; each high-speed burst starts and ends at LP-11 (C-203). The D-PHY section draws the sequence.

How far can a D-PHY or C-PHY link run?

MIPI positions both for camera and display links up to 4 m (C-199, C-201). The channel limits behind that, and the voltage levels, are in specifications only MIPI members can read; this page uses the public material and says where it does.

Can one device support both?

Yes. MIPI says C-PHY can share device pins with D-PHY, so a dual-mode PHY can run either on the same balls (C-200). A D-PHY with four data lanes and a clock lane uses ten wires and three C-PHY trios use nine, so the two fit in much the same footprint.

D-PHY: a forwarded clock and two speeds

D-PHY is source-synchronous. Beside one or more data lanes runs a clock lane, and the receiver samples each data lane with the clock that arrived alongside it (C-202). That is the simplest possible way to recover timing, and it makes one demand of the board: the clock and data lanes have to arrive together, so they are length-matched as a group.

The other thing D-PHY does is change speed. Between bursts each wire of a lane is driven on its own with a large, slow, single-ended swing, which costs almost nothing to hold; for a burst the same two wires become one small, fast differential pair. The low-power states are named by the levels on the two wires, and the way into a burst is a fixed walk through them (C-203).

A D-PHY data lane · low-power states into a high-speed burst and back

Two speeds on the same two wires. Between bursts the wires of a lane signal one at a time, with a large and slow swing; for a burst they become one small, fast differential pair. The way in is the walk LP-11, LP-01, LP-00, and every burst starts and ends at the LP-11 stop state (C-203). The voltages are drawn as shapes, not to scale: the levels are in the specification, which only MIPI members can read.

The walk into high speed is how the receiver knows a burst is coming without a separate wire to say so: the large single-ended levels are easy to detect even when the high-speed receiver is switched off. It also means a D-PHY receiver sees two different kinds of signal on the same pins, and its input has to handle both. In practice that means anything that loads the lane, such as a probe, can disturb the low-power handshake as well as the high-speed eye; that is engineering experience, not a published figure.

D-PHY v3.0 added a CTLE at the receiver (a continuous-time linear equaliser, which boosts the high frequencies the channel lost) and doubled the standard-channel rate to 9 Gb/s a lane, and v3.5 added an optional embedded clock, so a link can use the clock lane’s pins for data instead (C-201). At those rates D-PHY looks more like a SerDes, the serial links of PCIe and USB, than it used to, and the board has to treat it like one.

C-PHY: three wires, three levels, six states

A C-PHY lane is a trio of wires, A, B and C, and in every state one of them sits at a middle level while the other two are driven high and low. Three wires and one choice of which sits in the middle, then which of the other two is high, make six wire states: +x, −x, +y, −y, +z and −z (C-202). The receiver does not look at the wires one by one. It has three differential receivers, each comparing two of the wires (C-202):

The six C-PHY wire states, in steps of the mid-to-high level, and what each receiver sees
State	A	B	C	A − B	B − C	C − A
+x	high	low	mid	+2	−1	−1
−x	low	high	mid	−2	+1	+1
+y	mid	high	low	−1	+2	−1
−y	mid	low	high	+1	−2	+1
+z	low	mid	high	−1	−1	+2
−z	high	mid	low	+1	+1	−2

Three things in that table carry the whole design. The three receiver outputs always add up to zero, because (A − B) + (B − C) + (C − A) is zero whatever the wires do. No receiver ever sees zero: each sees a strong ±2 or a weak ±1, so every receiver has a definite answer in every state. And the six states give six different patterns of signs, so any change of state flips at least one receiver. That last point is the embedded clock: data is carried as a change of state, a symbol is one of the five other states to move to, and so every symbol produces an edge for the receiver to recover timing from (C-199, C-202).

The panel below builds that from the bits up. Type a 16-bit word in hexadecimal and watch it become seven symbols, each a number from 0 to 4 choosing the next state, then three wire voltages, then three receiver outputs. Before you start, predict what the eye of a C-PHY receiver looks like: an NRZ eye (two levels, the ordinary non-return-to-zero kind) has one crossing per edge, so how many should these receivers have, when some edges move by one step and some by three?

Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.

A trio, a symbol at a time analytical symbols — a trio — three trios — eye width —

The three wires · the state each symbol lands on, and the symbol

ABC

The three receivers

A−BB−CC−A

Their eye, folded over two symbols

The mapping from bits to symbols in the panel is a valid one, labelled as such: the word written as a seven-digit number in base 5, each digit choosing one of the five other states in a fixed order. The specification’s own table, and its description of each symbol as a flip, a rotation and a polarity (C-202), are members-only. Nothing the panel teaches depends on the table: any valid mapping gives a transition on every symbol, three levels, edges of two, three or four steps, and the same eye.

Why the C-PHY eye has more than one crossing

In an NRZ eye every edge goes from one level to the other, so every edge crosses zero at the same point in its rise. A C-PHY receiver’s edges come in sizes. Going from −1 to +1 is a two-step edge; from −1 to +2, or −2 to +1, a three-step edge; from −2 to +2, four steps. With a fixed edge time, each of those crosses zero at a different moment, so the receiver sees a spread of crossing times even on a perfect channel. That spread is a jitter that the code itself creates, and it is why a C-PHY eye is read with its own conventions rather than as three NRZ eyes laid on top of each other.

Slower edges widen the spread, which is what the slow-edges preset shows. Loss does too, and it takes the weak level first: a ±1 that has to climb out of a −2 is the slowest to arrive.

Routing a trio is not routing a pair

In a differential pair, a length mismatch between the two wires turns part of the signal into common mode and, much later, starts to close the eye. In a trio there is no common mode to absorb it: the three receivers compare every wire with both of the others, so a late wire moves the crossings of two receivers at once and spreads them further. The skewed-wire preset delays one wire by a fifth of a symbol and the eye loses a sizeable share of its width. The practical rule that follows is engineering practice rather than a published figure: match the three wires of a trio to each other as you would the two wires of a pair, and route them as a group, with the same reference and the same neighbours.

What C-PHY saves is the clock lane and the matching between lanes. Each trio carries its own timing, so one trio can arrive a little later than another without harm, which loosens the inter-lane matching that a D-PHY clock-and-data group needs.

Why this decides how your board behaves

D-PHY sees two kinds of signal on one pair. Anything that loads the lane, a probe or a test pad, can upset the low-power handshake as well as the high-speed eye, so check both.
D-PHY needs its group matched. Clock and data arrive together or the sampling point moves; at 9 Gb/s a lane the unit interval is 111 ps, so a few picoseconds of mismatch is already a measurable share of it.
C-PHY needs each trio matched to itself. A late wire costs eye width in two receivers at once.
C-PHY’s eye is not an NRZ eye. Its crossings spread with the edge time and the loss, and its measurement conventions are its own.
A dual-mode footprint has to serve both. The same balls carry four pairs or three trios, so the escape and the matching rules have to satisfy whichever mode the product ships (C-200).

What to do about it

Match a D-PHY clock lane to its data lanes as a group, and keep the pairs coupled and on one reference.
Match the three wires of each C-PHY trio to each other, and route them together with the same spacing to their neighbours, so no wire couples differently from the others.
On a dual-mode design, apply the stricter of the two rule sets to every wire that can be either.
When measuring, check the low-power handshake as well as the burst: probe loading and slow LP edges fail there first.
For the electrical limits and the channel definitions, use the PHY vendor’s layout guide: the specifications that hold them are members-only.

Go deeper — the code’s arithmetic, what “embedded clock” buys, and what is not sourced here

The code’s arithmetic. Five possible next states per symbol give log₂5, about 2.32 bits a symbol, as the most a symbol could carry. Seven symbols have 5⁷ = 78,125 sequences, enough for every one of the 65,536 sixteen-bit words, with 12,589 left over; six symbols have only 15,625, not enough. So 16 bits in 7 symbols, 16/7 = 2.29 bits a symbol, is the fewest symbols that hold a 16-bit word, at 98.4% of the ceiling. At 6 Gsps a trio then carries 6 × 16/7 = 13.7 Gb/s, and three trios 41.1 Gb/s, the “about 41 Gbps” MIPI quotes (C-199).

What the embedded clock buys and costs. Because every symbol changes the state, every symbol changes at least one receiver’s sign: the six states have six different sign patterns, so moving between any two of them flips at least one. A clock-recovery circuit therefore never goes a symbol without an edge, and needs no run-length limit or scrambler to guarantee one. The cost is the crossing spread above: the timing information arrives on edges of different sizes, which is a jitter the receiver’s clock recovery has to live with.

The 18-wirestate mode. C-PHY v3.0 added a multi-phase coding with 18 wire states, at up to 5 Gsps for 17.8 Gb/s a trio (C-199). That is 3.56 bits a symbol, more than the 2.28 of the six-state code, consistent with more distinct states per symbol rather than a faster symbol rate. Its coding is not described in the public material this page uses, so the panel stays with the six-state mode.

What is not sourced here. MIPI keeps the D-PHY and C-PHY specifications for members, so the voltages, the timing parameters of the low-power handshake, the channel models and the mapper table are not on this page. Rates and features come from MIPI’s own public pages, the coding structure from a PHY IP vendor’s description, and the low-power entry sequence from a device datasheet, each recorded in the claim ledger with what it can and cannot establish.

In the real world

D-PHY and C-PHY carry almost every camera and display link in a phone, and increasingly in cars, drones and robots, usually through CSI-2 for cameras and DSI-2 for displays (C-199, C-201). The links are short, but they cross flex circuits and connectors, run beside RF and power, and spend much of their time switching between sleeping and bursting.

The practical differences are the ones this page has drawn. A D-PHY board is a matching problem across a group and a handshake problem at every burst; a C-PHY board is a matching problem inside each trio and an eye that has to be read on its own terms. The pins are often the same, so the routing has to be right for both.

Sources

Rows marked with a claim id are tracked in the claim ledger, which records what each source can and cannot establish.