LPDDR5 vs LPDDR5X: WCK Clocking, Training and Signal Integrity

At a glance

LPDDR5 vs LPDDR5X: what is the difference?

LPDDR5X is an optional extension of LPDDR5, defined in the same JEDEC standard, JESD209-5, from its 2021 revision onwards (C-165). It adds the 7500 and 8533 MT/s speed bins and, for the channel, transmit pre-emphasis, per-pin decision feedback equalisation (DFE) in the DRAM, receiver offset calibration and a stricter termination rule for dual-rank reads (C-167). LPDDR5 itself tops out at 6400 MT/s (C-2b). The pins and signalling do not change. LPDDR5 vs LPDDR5X sets the two side by side, row by row, and the generations table adds LPDDR4X and LPDDR6.

How fast is LPDDR5X?

JESD209-5B (July 2021) extended the standard to 8533 MT/s (C-2a), and the 7500 and 8533 bins are the ones sold as LPDDR5X (C-167). Vendors have since gone further: Samsung announced a 10.7 Gb/s LPDDR5X in April 2024 (C-169). A 16-bit channel at 8533 MT/s moves 17.1 GB/s, and at 10.7 Gb/s 21.4 GB/s; a wider interface multiplies that, as the bandwidth table shows. The current edition, JESD209-5C, is sold by JEDEC, so which bins above 8533 it defines is not quoted here.

What clocks does LPDDR5X use?

Two, plus a read strobe. CK carries command and address. WCK, forwarded by the controller, times write data and runs four times as fast as CK above 3200 Mb/s (twice as fast below). Reads come back timed by RDQS, a strobe from the DRAM. There is no bidirectional DQS as on LPDDR4X (C-4a). At 8533 MT/s CK runs at 1066.5 MHz and WCK at 4266.5 MHz, and data moves on both edges of WCK (C-167). The clocking figure draws one CK cycle.

What voltage does LPDDR5X use?

The I/O supply, V_DDQ, is 0.5 V, with a 0.45 V option and 0.3 V when the termination is off at low speed, and the I/O standard is LVSTL (C-53). JEDEC gives LPDDR5 a signalling voltage of 250 mV (C-166), and the core rail runs at 1.05 V, or 0.9 V when voltage scaling lowers it (C-63). For comparison, LPDDR4X ran its I/O at 0.6 V (C-168).

Does LPDDR5X need training?

Yes. Before it can move data reliably the controller sets the reference voltages, trains the command bus, levels WCK against CK (WCK2CK leveling) and then trains the read and write data against their clocks; LPDDR5X adds a receiver offset calibration, recommended at every power-up (C-5). Why training is the whole story explains what it can and cannot fix.

How long can an LPDDR5X trace be?

The limits come from the SoC vendor’s guide, because the standard sets the pin-level timing and leaves the channel to the system. As one public example, an FPGA vendor routes LPDDR5 data as 40 Ω stripline on the upper layers, at most 3.0 inches in total (C-170). A phone is usually far shorter, and with the DRAM stacked on the processor package there may be no board trace at all.

Is LPDDR5X always soldered down?

Usually, but no longer always. JEDEC’s CAMM2 standard (JESD318, 2023) puts LPDDR5/5X on a compression-attached module for notebooks and some servers (C-54), which adds a connector to a channel that used to have none (C-3). LPDDR5X on a module covers what that changes.

How is LPDDR5X different from DDR5?

Mostly in where it lives, and the electrical choices follow from that. LPDDR5X sits beside the processor, on its package or on a short CAMM2 module; DDR5 sits on modules in sockets, with commands and clock routed fly-by along the DRAMs (C-43), and a channel can carry two modules (C-52). So LPDDR5X can afford LVSTL at a V_DDQ of 0.5 V on 16-bit channels with a separate write clock (C-53), while DDR5 keeps a 1.1 V pseudo-open-drain bus (C-37), two 32-bit sub-channels per module (C-44) and a 4-tap DFE in every DRAM (C-40), with timing defined to 8800 MT/s (C-35). The DDR5 page sets the two side by side.

The panel above is a budget, not a simulation: each slider is one thing that spends part of a bit, and what is left is what the DRAM’s receiver gets. Before you touch it, guess which term you would argue about first in a design review. Then switch training off, or step the rate up to 10.7 Gb/s, and see whether the answer changes.

Parallel and source-synchronous, and why that changes everything

Almost everything else on this site is a serial link: one differential pair, with the clock recovered from the data itself. A DRAM interface is the opposite. Sixteen single-ended data wires per channel switch together, and a separate clock travels beside them to tell the receiver when to sample. Differential data would double the pin count, which a phone cannot afford, so only the clocks get a pair.

Sending the clock with the data is called source-synchronous, and it has one large advantage: anything that delays the data and the clock equally cancels. What does not cancel is difference. Skew between a data bit and its clock, or between one bit and the next, spends budget directly. So a DRAM channel is mostly about everything that makes one wire different from another.

CK, WCK and RDQS: why LPDDR5X has two clocks

Up to LPDDR4X the command clock CK ran at the same frequency as the data strobe DQS, which itself went both ways: driven by the controller on writes and by the DRAM on reads (C-168). That forced the command and address bus to keep up with the data. LPDDR5 split the job. CK slowed down and carries only command and address; a new write clock, WCK, carries the data rate; and reads get their own strobe, RDQS, driven by the DRAM (C-4a, C-166).

Two consequences follow for the board. First, the hard timing problem shrinks to the data byte and its clock, which is a small, local group of wires. Second, source-synchronous timing only cancels delay for signals that travel together, and writes and reads travel in opposite directions. A single shared strobe would cancel in one direction and not the other, which is why reads come back with a strobe launched by the DRAM. RDQS is optional at low speed, where a read can run strobe-less or with a single-ended strobe, and it is differential at high speed (C-4a).

LPDDR4X vs LPDDR5 vs LPDDR5X vs LPDDR6, side by side

Read the unit-interval row first. Every generation has cut it, and LPDDR5X at 10.7 Gb/s already reaches the bit length where LPDDR6 starts. The voltage row barely moves after LPDDR5, so each step leaves the same half-volt swing less time. The last two rows are the response: equalisation and better-behaved termination arrive just as the bit gets short enough to need them.

LPDDR5 vs LPDDR5X: what actually differs

Less than the name suggests. LPDDR5X is not a new standard but an optional extension written into the same JEDEC document as LPDDR5 (C-165). The pins, the signalling and the clocking scheme are the same. What LPDDR5X adds is two faster speed bins and the handful of features needed to make them work. Before reading the table, try a prediction: if the pins and voltages do not change, where would you expect the differences to show up?

So the differences sit exactly where a shorter bit would put pressure: in equalisation, in termination on a shared bus, in calibrating the receiver, and in giving the DRAM core more clock cycles for the same nanoseconds. For the channel, four of them matter:

• Transmit pre-emphasis. Programmable per byte lane, to make up for loss in the channel (C-167). That is a quiet admission that at 8533 MT/s the short channel is no longer lossless.
• Per-pin DFE in the DRAM. LPDDR5 already had a single-tap DFE on write data (C-168); LPDDR5X allows it to be set pin by pin. Both equalisers are optional, and each device says in its mode registers whether it has them (C-53).
• Unified non-target ODT. On a dual-rank bus the rank that is not being read still hangs on the data net. LPDDR5X requires every device to terminate it the same way, to protect read signal integrity at speed (C-167).
• Receiver offset calibration. A training step that trims the DRAM receiver’s DC offset, recommended at every power-up (C-5, C-167).

Is LPDDR5X backward compatible with LPDDR5?

At the level of the standard they are one family: same document, same pins, same signalling. When JEDEC published LPDDR5X, Samsung described it as a large bandwidth gain “with minimal IP change” (C-165). That is a member’s description, not a guarantee. Whether a particular controller and PHY support both, and at which bins, is in their own documentation. For a board the more useful question is a different one: a layout that was signed off at 6400 MT/s had a 156 ps bit, and at 8533 it has 117 ps. Same pins, about a quarter less time per bit, so the margin has to be shown again at the new rate rather than inherited.

LPDDR5X bandwidth by interface width

Peak bandwidth is plain arithmetic: transfers per second on each pin, times the number of data pins, divided by eight for bytes. One LPDDR5X channel is 16 bits wide. A phone or laptop processor runs several channels side by side, and an LPDDR5/5X CAMM2 is 128 bits, eight x16 sub-channels (C-171). Pick the row for the rate and the column for the width.

These are ceilings, not what a benchmark will report. Refresh, the turnaround between reads and writes, bank conflicts and, where enabled, link ECC all take transfers that carry no user data, so sustained bandwidth sits below the table. Before you compare two systems, check that both quote the same width: a figure for one channel and a figure for the whole processor can differ by a factor of eight at the same data rate.

The channel

Point to point, controller to DRAM, with no fly-by topology: routed on the board, stacked on the processor package, or, since CAMM2, through a module connector (C-3, C-54). A dual-rank configuration, or two dies sharing one channel, puts more than one device on the same data net, which is what non-target ODT exists for. Check the configuration before assuming the simple case.

Short for loss is not short for reflections, and the arithmetic is worth doing. At roughly 6.7 ps/mm, a 10 mm net is 67 ps one way and 134 ps per round trip; a 30 mm net is 201 ps and 402 ps. At the 3.0-inch limit in the FPGA guide (C-170), the round trip is about 1020 ps, nearly 8.7 bits. Against a 117 ps bit, even a short net’s first reflection arrives one or more bits late, and a second and third follow it. Reflections here are survivable not because they are fast but because they are small: the impedance steps on a controlled point-to-point net are modest, and on-die termination absorbs most of what comes back. Remove the termination, or add a stub, and the timing cost appears at once.

What you get instead is density. Sixteen data lines plus clocks and command signals, escaping a fine-pitch BGA as a tight bundle, all switching within the same few hundred picoseconds.

LPDDR5X on a module: CAMM2

For most of its life LPDDR was soldered down, and the capacity was fixed when the board was built. JEDEC’s CAMM2 standard, JESD318 (December 2023, now revision B), changed that: it defines compression-attached modules for both DDR5 and LPDDR5/5X on a common connector design, with different pinouts and deliberately different mounting so that a module cannot be fitted where the other kind belongs (C-54). The connector has its own performance standard, PS-007A, written for channels beyond 6.4 GT/s (C-179), which JEDEC presents as better for signal integrity and RF interference than a DDR5 SODIMM connector, at half the footprint (C-172).

For the channel, a module brings back three things the soldered-down case did not have. Predict them before reading on, using what this page has said about reflections and termination.

• A discontinuity. The connector and the vias on both sides of it are an impedance step in the middle of the net, and on a bus with no stub resistors (C-176) the on-die termination is what absorbs the echo. The standard’s own simulation example puts 40 mm of motherboard in front of the connector (C-176): a round trip of about 535 ps, or 4.6 bits at 8533 MT/s, before the module’s routing is counted.
• More length. The module’s own routing adds to the mainboard trace, which moves the net toward the loss that LPDDR5X’s pre-emphasis and DFE were added for (C-167).
• Possibly a second rank. A two-rank module puts two devices on each data net, and that is exactly the case unified non-target ODT was made for (C-167, C-171).

Matching through a connector

An edge-connector module has its pins in two rows, so the motherboard and the module can each be matched on its own. A CAMM2’s pins form an array of 14 rows, and one data byte can span several of them. Matching each board separately would then add serpentines on both sides to cancel a difference the other side already has. JESD318B instead gives each row a 1 mm length offset, so that the whole path, board plus connector plus module, is what gets matched (C-177).

On the module itself, the standard’s LPDDR5/5X bounds are tight in some places and loose in others (C-177). Each data bit stays within 0.6 mm of its byte’s read strobe, about 4 ps at 6.7 ps/mm, while the data-to-WCK window is 5.2 mm wide, about 35 ps. The bits within a byte are matched to under 0.025 mm, and the two halves of each differential pair to under 0.05 mm. Those are module-side numbers; the rules for the full channel come from the SoC supplier.

Vias, crosstalk and the ground under the connector

The layout rules read like a summary of the crosstalk section below. Signal vias are kept apart, with power or ground vias between them, and the vias of different channels sit at least 2 mm apart (C-178). Ground vias sit close to the signal vias so that return current has a short path. Under the connector the standard asks for a solid ground plane with no traces in it. The ground shields that some connector variations carry break at points that differ from one supplier to the next, and a trace crossing that area could line up with a gap (C-174).

One rail or two: VDDQ on a module

The module’s own PMIC makes the DRAM rails from a 5 V input, which raises a power-integrity question that a soldered-down design never had: who makes V_DDQ? JESD318B allows two answers (C-175). In the split-rail method, which every module must support, the SoC and the DRAM each have their own regulator. That is simple, but each regulator only promises to stay within its tolerance, so one can sit at the top of its band while the other sits at the bottom, and the I/O swing, which depends directly on V_DDQ, loses that much margin. In the optional common method one regulator on the motherboard feeds both, which removes the mismatch but splits a single tolerance between the board and the module. The host must then hold V_DDQ between 0.477 and 0.577 V at the module footprint, a 100 mV window around 0.507 V that already sets aside 7 mV for the drop across the connector and the module’s planes.

What the connector itself must meet

PS-007A measures the connector as it is used: with its pads and the 0.25 mm micro-vias on both boards, at a 40 Ω reference, out to 20 GHz (C-180). The interesting part for LPDDR5X is the band around its Nyquist frequency, half the transfer rate: 4.27 GHz at 8533 MT/s and 5.35 GHz at 10.7 Gb/s. Before looking, guess which of loss, reflection and crosstalk the limits leave largest there.

Read the last column as a sense of scale, not an eye penalty: it is how large a sine at the Nyquist frequency the limit lets the connector lose, send back or couple across, against JEDEC’s 250 mV signalling level (C-166). Loss is almost nothing, under 5%. The reflection is the big term: a connector that just meets the return-loss limit sends back a tenth of the wave, and on a bus without stub resistors that echo lands bits later, on the data, unless the termination absorbs it. Crosstalk per aggressor is a few millivolts, but a byte has many aggressors, which is why the standard also limits the power sum. In the time domain the same connector must stay between 40 and 45 Ω for a 40 ps edge (C-180); a step from 40 to 45 Ω alone reflects about 5.9%.

None of this makes a module unworkable. It means a CAMM2 design is signed off as a connectorised channel, with the connector, the module and its power delivery in the model, rather than borrowed from a memory-down layout. The module’s own impedance profile is documented in each reference design’s annex, which this page has not read.

Where the margin actually goes

• Crosstalk. Sixteen neighbours in a dense escape, with far-end coupling arriving as the data edge does. The vias count as much as the traces: one vendor’s LPDDR5 guide warns that deep-layer via transitions add vertical coupling and so more crosstalk, and keeps the data on upper layers (C-170).
• Simultaneous switching noise (SSN). A byte switching together pushes a large di/dt through shared return inductance and moves the reference the receiver compares against. Data bus inversion, flagged on the DMI pins, lets the transmitter invert a byte to limit how many lines change or draw current at once (C-63); which rule a given mode uses is set in the standard.
• Reflections from the package, the escape vias and any stub, arriving bits late as the arithmetic above shows. Termination and drive strength are both programmable, and ZQ calibration keeps them on value as the die warms (C-166).
• The DRAM’s own WCK-to-DQ offset. Inside the DRAM the data path and the clock path are different circuits, so their delay differs part to part and drifts with voltage and temperature. That is not a channel effect at all, and no board work removes it; training does.

Sign-off

At these rates the DRAM’s write receiver is specified by an eye mask, a keep-out region in voltage and time that the signal at the pin must stay out of, with matching limits on the controller’s transmitter. The numbers are in JESD209-5, which JEDEC sells, so this page does not quote them. Sign-off means showing the mask is respected across process, voltage and temperature corners, with worst-case crosstalk patterns, realistic SSN, any equalisation the devices support switched on, and a package model that includes the return network.

The practical trap: simulate the data bus alone and it passes comfortably. The failures live in the combinations: the worst aggressor pattern and maximum simultaneous switching and the fast-strong driver corner. Any two of those is usually fine.

Why this decides how your board behaves

• Skew is the currency, not decibels. Length matching, via count, layer assignment and glass weave matter more than laminate choice, though from 8533 MT/s loss is large enough that the devices added equalisation for it.
• Many bits switch together, so SSN is a first-class impairment. Sixteen outputs changing in the same picosecond is exactly the case on Simultaneous Switching Noise and Ground Bounce, and it is why the quiet bit is the one that fails.
• Crosstalk is bus-wide. Every victim has neighbours on both sides, and the worst case is all of them switching the same way at once.
• The interface is trained, so the board’s job is to be trainable. Training can centre a clock in an eye; it cannot fix a discontinuity or a coupling.

What to do about it

Match within a byte lane tightly and between lanes loosely. Each byte has its own clock pair, so the tight constraint is within a byte, and it includes the package routing as well as the board (C-170). Matching the whole bus to the same tolerance spends routing effort for nothing.

Keep the data on shallow layers and give the return path as much attention as the trace. Every layer change on a bus this wide multiplies, the returns share openings, and deep via transitions couple vertically (C-170).

Keep the power delivery close and the pin distribution even. SSN is set by shared inductance, which is a pinout and package property more than a board one.

Read the training results, not just the pass/fail. Where training landed, how far from centre and how much eye it found, is the margin information, and the controller has it without any instrument.

In the real world

LPDDR sign-off is dominated by two things that are decided before layout: the pinout and the package. Everything the board designer can do is bounded by how much shared inductance the package presents and how the byte lanes map onto physical positions.

That makes the early conversation the valuable one. Once the ballout is fixed, the remaining levers are length matching and return paths: necessary, and much smaller than the decisions already made. And as rates pass 10 Gb/s, the trend in the table holds: the devices bring more of their own equalisation and termination control, and the board’s job is to stay within what those can correct.

Related

• LPDDR6 Signal Integrity: Wide NRZ and Sub-Channels, the next generation: 24 data pins a channel at 10.7 to 14.4 Gb/s
• DDR5, the module-based cousin, set side by side with LPDDR5X on that page
• PCB Crosstalk: NEXT, FEXT, and Mutual Coupling
• Simultaneous Switching Noise and Ground Bounce
• Termination Schemes: Series, Parallel, Thevenin and AC
• BGA Escape Routing and Breakout Congestion