SI in practice / 05
IBIS, IBIS-AMI, and SPICE Model Selection
A link simulation needs models of the devices at both ends, while transistor-level details are rarely distributed. The industry therefore uses three levels of abstraction, each trading accuracy for speed and for how much the vendor has to reveal. Knowing which level answers which question saves a great deal of time.
Init takes the channel's impulse response and returns a modified one — a purely LTI operation, which is exactly what a statistical flow needs. GetWave processes a real waveform and can be as non-linear as it likes, which is what a time-domain flow needs. What a model's flags declare it will do — whether Init returns a modified impulse response, and whether the waveform path is used — is what decides which simulations you can run, so check the flags rather than inferring from the entry points.When validating multi-gigabit interconnects, hardware engineers face a fundamental modeling dilemma. Transistor-level SPICE schematics represent proprietary intellectual property that semiconductor vendors strictly refuse to disclose. Furthermore, running full transient SPICE simulations across millions of bits on a 32 Gbps backplane is computationally intractable — a single simulation would take weeks to execute.
Classic IBIS (I/O Buffer Information Specification) solved the IP-protection and speed challenges for legacy parallel interfaces (like DDR, PCI, or flash memories) by replacing transistor netlists with table-driven current-voltage (I-V) curves, voltage-time (V-t) switching tables, and basic package parasitics. However, classic IBIS completely breaks down for modern multi-gigabit SerDes: it treats the buffer as a static analog impedance and has zero mechanism to represent digital signal processing (DSP), feed-forward equalization (FFE), continuous-time filters (CTLE), decision feedback loops (DFE), or clock-data recovery (CDR).
IBIS-AMI (Algorithmic Modeling Interface) was created to bridge this architectural divide. It splits the transceiver into two distinct domains: a standard IBIS analog buffer representing pad capacitance and termination, coupled to compiled, platform-native binary dynamic link libraries (DLLs or shared objects) that execute the vendor's proprietary DSP algorithms at hardware speeds. Understanding how SPICE, classic IBIS, and IBIS-AMI trade off speed, architectural visibility, and analog fidelity is essential to choosing the right tool for each phase of design sign-off.
Why models exist in layers
To simulate a channel you need to know what the driver does and what the receiver does. The obvious answer — use the actual circuit — fails for two reasons at once.
It is too slow. A transistor-level simulation of a SerDes running millions of bits is not a thing you do overnight. And you need millions of bits, because that is what an eye is made of.
It is commercially impossible. A driver's netlist is among the most sensitive IP a silicon vendor has. No amount of asking will produce one.
So the industry built abstractions: descriptions detailed enough to predict behaviour and abstract enough to share. Each layer keeps what matters for a class of question and discards the rest.
Three levels
- IBIS. A behavioural description of the analogue buffer: V-I curves for the pull-up and pull-down, V-T curves for the switching behaviour, package parasitics, and die capacitance. Fast, portable, and reveals nothing about the transistors. It represents the driver and receiver front end, and nothing else — an IBIS model has no concept of equalisation.
- IBIS-AMI. IBIS plus compiled shared libraries that model the transmitter and receiver algorithms — FFE taps, CTLE response, DFE adaptation, CDR behaviour. This is what makes modern serial link simulation possible at all, because the equalisation is most of the link and vendors will not publish it in readable form.
- SPICE / transistor-level. The actual circuit. Most accurate, slowest by orders of magnitude, and commercially sensitive enough that it is usually delivered encrypted if at all. Reserved for questions the behavioural models cannot answer.
AMI_Init and AMI_Close bracket
the model's life and are not optional — they are how it is created and destroyed. What varies is
the processing behaviour, and the model declares that in its flags rather than by which
functions happen to exist.
Two behaviours matter. Does
AMI_Init return a modified impulse response, or
does it merely initialise and leave the channel alone? That is what a statistical flow depends
on. And is the waveform path actually used, so the model can be non-linear and time-varying? That
is what a time-domain flow depends on. A model may be usable in one flow, the other, or both —
but read that off the flags and the accompanying documentation, not from the presence of a symbol
in the library. Check against the
IBIS specification edition the model claims.
Where models mislead
Model problems are a large share of channel-simulation problems, and they share a signature: the result looks entirely reasonable.
- Corners that do not exist. IBIS ships typ/min/max curves, and it is easy to combine a fast driver with a slow receiver in a way silicon never produces. Worse, running typical only is the most common mistake — the fast-strong corner has both a lower output impedance and a faster edge, which makes reflections and crosstalk worse simultaneously.
- An AMI model tuned for its own reference channel. Adaptive blocks converge against what they are given; a model validated on a smooth channel can behave oddly on one with a resonance.
- Package parasitics counted twice. If the IBIS package model and the extracted package S-parameters both include the same balls and traces, the channel is longer than reality by one package. This is common enough to be worth checking every time.
The practical sequence: IBIS for pre-layout topology and termination work, where speed matters and equalisation is not yet the question; AMI for everything to do with a serial link's real margin; transistor-level only for the specific effect nothing else reproduces, and budget the runtime before you promise the result.
Sources
- IBIS 8.0 specification — AMI lifecycle, entry points and model flags
Why this decides how your board behaves
- The model level decides which questions you can even ask. An IBIS model has no concept of equalisation, so it cannot answer anything about a modern serial link's margin. Choosing the wrong level does not give a wrong answer — it gives a confident answer to a different question.
- Most of a modern link is in the AMI part. The equalisation and clock recovery do more to the eye than the channel does, so a channel simulation without them is not a simulation of the link.
- Model validity limits are rarely stated and always exist. Every model was extracted under conditions — a load range, a voltage, a temperature, a data rate — and is not guaranteed outside them.
- Corners matter as much as typical. A model delivered with only a typical corner cannot support a sign-off that has to cover fast-strong and slow-weak.
What to do about it
Ask what the model was validated against, not just what it contains. The useful question to a vendor is "what measurement or transistor-level result was this checked against, and over what range?" A model that has never been correlated is a document, not a prediction.
Check the corners are present and use them. Fast-strong is where reflections and crosstalk are worst; slow-weak is where timing is worst. A typical-only run covers neither.
Sanity-check the simple things before trusting the complex ones. Does the IBIS model's V-I curve give the output impedance you expect? Does its V-T curve give the rise time the datasheet quotes? Those take minutes and catch a surprising fraction of bad models.
Reserve transistor-level for questions the others genuinely cannot answer. Non-linear behaviour, unusual loading, or an interaction outside the chosen abstraction — those justify it. Ordinary channel margin does not.
- Simulation and hardware disagree, and the channel model is verified. Look at the buffer models next. A wrong output impedance or rise time moves everything downstream.
- Results that change dramatically with a small change in load. Possibly outside the model's extraction range. Check what load it was characterised into.
- An AMI model that behaves identically regardless of the channel. Its adaptation may not be running — many models need to be given enough symbols to converge and will silently report their initial state if not.
- Different simulators giving different answers with the same files. Usually a difference in how the AMI flow is driven — block size, bit count, or whether the statistical or time-domain path was taken.
Go deeper — what each layer contains, the AMI Init/GetWave architecture, and model modes
IBIS is a behavioural description of the analogue buffer: V-I curves for the pull-up and pull-down, V-T curves for the switching behaviour, package parasitics and die capacitance. It represents the driver and receiver front end and nothing else. It is fast, portable, and reveals nothing about the transistors — which is why vendors publish it.
IBIS-AMI adds compiled shared libraries that model the transmitter and receiver algorithms: FFE taps, CTLE response, DFE adaptation, CDR behaviour. The algorithms are in binary form, so the vendor's implementation stays private while its behaviour is available. This is what makes modern serial link simulation possible at all.
SPICE / transistor-level is the actual circuit: most accurate, slowest by orders of magnitude, and usually delivered encrypted if at all.
The IBIS-AMI API: Init vs. GetWave. An IBIS-AMI model consists of three distinct files:
a standard .ibs file declaring the analog electrical buffer (C_comp, package RLC, termination),
a .ami text configuration file declaring user parameters and algorithmic flags, and a compiled
shared library (.dll on Windows or .so on Linux) exposing two primary C API entry points:
AMI_Init(The Impulse / Statistical Entry Point): Called once before the simulation begins. The EDA simulator passes the combined analog channel impulse response (the LTI cascade of TX analog buffer, S-parameter interconnect, and RX termination). If the model declaresInit_Returns_Impulse = True, the function processes the impulse through its linear filters (such as FFE or ideal CTLE) and returns a modified impulse response to the simulator. This modified impulse is what powers rapid statistical eye synthesis down to 10-12.AMI_GetWave(The Time-Domain / Waveform Entry Point): Called iteratively during transient bit-by-bit simulation. The simulator chunks the transmitted bitstream into sequential waveform blocks (e.g. 10,000 samples) and feeds them intoAMI_GetWave. Inside this function, the vendor's compiled code runs non-linear DSP: dynamically adapting CTLE gain, adjusting DFE feedback taps via Least Mean Squares (LMS) logic, and simulating the Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) tracking. It returns modified analog samples alongside an array of recovered clock tick timestamps.
Statistical vs. Bit-by-Bit model flags. The declared flags in the .ami file
dictate what simulation modes are mathematically permissible:
- Dual-Mode Models: Both
Init_Returns_Impulse = TrueandGetWave_Exists = True. These support both statistical and time-domain flows. However, the two modes often produce divergent results:AMI_Inittypically evaluates an idealized, perfectly converged equalizer, whileAMI_GetWavemodels the real-world quantized adaptation loop, noise penalties, and finite settling times. - GetWave-Only Models:
Init_Returns_Impulse = FalseandGetWave_Exists = True. Common in modern SerDes with highly complex non-linear digital DSP or ADC-based architectures. These models cannot be used in statistical mode; they mandate time-domain bit-by-bit runs. - Init-Only Models:
GetWave_Exists = False. Restricted to linear equalizers (pure FFE / linear CTLE). They cannot represent dynamic DFE adaptation or CDR cycle-slipping.
Practical simulation pitfalls. Two operational rules are mandatory when running AMI flows:
- Burn-in and settling periods: Because
AMI_GetWavemodels live silicon adaptation, the first 100,000 to 500,000 bits are consumed by the CDR acquiring phase lock and the DFE taps hunting for convergence. Always discard these initial warm-up bits; evaluating eyes during the convergence transient will report a completely closed, false-failing link. - Impulse response truncation: In statistical mode, if the EDA tool truncates the channel
impulse response before all trailing reflection echoes have died down,
AMI_Initwill silently omit return-loss ripples, yielding an overly optimistic eye diagram.
In the real world
Model quality is the most common limiting factor in channel simulation accuracy, and it is the part least under your control. The channel you can model well — it is copper and you can measure it. The chips you take on trust.
Which makes the relationship with the silicon vendor part of the engineering. The questions worth asking early are which corners exist, what the models were correlated against, and whether the AMI implementation supports both flows. Discovering the answers during a debug is considerably more expensive than asking at the start.
Related
Sources
Rows marked with a claim id are tracked in the claim ledger, which records what each source can and cannot establish.