SIPI

Interface sign-off / 04

USB 3.1 and 3.2 Signal Integrity: SSC and Compliance

By Geetansh Arora — Principal SI/PI Engineer9 min

USB is the interface where you do not own the channel. The board is yours; the connector, the cable and whatever is at the far end are not. That inverts the usual priorities — the rates are undemanding, and the engineering is about tolerating variation you cannot characterise.

Two problems PCIe does not have
SSC is mandatory — and the receiver pays for it nominal −5000 ppm clock wanders down-spread at tens of kHz emissions energy spread instead of a narrow spike so the CDR must track a moving clock — simulating with a fixed clock omits a real term and half the channel ships with the user host device unknown length and quality Type-C Type-C reversible — so a mux or redriver sits in the signal path, adding its own loss design against the worst compliant cable, not a typical one
USB's distinguishing SI problem is not its data rate. At 5 and 10 Gbps the unit intervals are 200 and 100 ps — undemanding next to Gen 5. It is that half the channel is a cable the user bought and plugged in either way up. Spread spectrum is mandatory: the clock is modulated roughly 0 to −5000 ppm at a rate in the low tens of kilohertz, which spreads emissions energy across a band instead of concentrating it in a spike. The cost lands on the receiver — the CDR must track a continuously moving clock, so SSC tracking is a real part of the jitter budget, and a simulation with a fixed-frequency clock has omitted a term the specification assumes is there. Type-C reversibility is a signal-integrity cost paid for a usability feature: the SuperSpeed pairs land on either of two pin sets, and whatever resolves that sits directly in the path. Compliance is a defined test, not an in-house flow — the transmitter is measured through a reference channel, and the receiver is fed a deliberately stressed signal and must hold its error rate.

Universal Serial Bus (USB) is by far the most ubiquitous high-speed digital interface on the planet. Whether connecting a workstation to an external NVMe drive, an ultra-HD webcam, or a mobile phone, USB 3.x (5 Gbps Gen 1, 10 Gbps Gen 2, and 20 Gbps Gen 2×2) is the multi-gigabit interconnect that almost every hardware engineer is tasked with routing and certifying.

Yet USB presents a brutal design reality that internal enterprise links (like PCIe server backplanes or LPDDR memory buses) never face: you do not own the channel. In a closed-box system, the entire physical path between transmitter and receiver is modeled, routed, and bounded within your chassis. With USB, your circuit board terminates abruptly at a surface-mount Type-C receptacle. The remaining two-thirds of the channel is a cheap, twisted, two-metre cable bought by an end-user from an unknown vendor, plugged in upside-down, and connected to an uncharacterized peripheral.

To make true plug-and-play interoperability possible across billions of devices, the USB Implementers Forum (USB-IF) established the industry's most rigorous, publicly standardized compliance framework. A USB 3.x port cannot assume clean conditions: it must survive mandatory Spread-Spectrum Clocking (SSC) to pass FCC emissions, absorb the parasitic losses of reversible Type-C crossbar switches, and prove receiver jitter tolerance against standardized "worst-compliant" test fixtures.

Designing for a channel you have never seen

Every other interface on this site is a channel you can measure. A PCIe link lives entirely inside a product; an LPDDR bus is a few centimetres of your own board. You can build it, characterise it, and sign it off.

A USB channel is your board, then a connector, then a cable of unknown length and quality made by someone you have never met, then a device you have never seen. Two thirds of it is outside your control and outside your knowledge.

So the design target is different. It is not "make this channel good" — you cannot. It is "leave as much margin as possible for the part you do not control", and that reframing drives every decision below.

What it is

A differential serial link with an embedded clock, defined by USB-IF at 5 Gbps (Gen 1, 8b/10b), 10 Gbps (Gen 2, 128b/132b) and 20 Gbps as two 10 Gbps lanes (Gen 2×2). Unit intervals of 200 ps and 100 ps respectively — undemanding next to PCIe Gen 5, which is fortunate, because the channel is much less controlled.

The channel you don't own

A PCIe channel is entirely inside a product. A USB channel is a board, a connector, a cable of unknown length and quality, another connector, and another board. The cable is frequently the largest single term in the loss budget and it is chosen by the user after the product ships. Design has to close against the worst compliant cable, not a typical one.

Type-C adds a second complication that is easy to underestimate. The connector is reversible, so the SuperSpeed pairs appear on either of two pin sets depending on orientation. Something has to resolve that — a mux, a redriver, or a device with both pairs wired — and whatever it is sits directly in the signal path adding its own loss and discontinuity. Reversibility is a signal-integrity cost paid for a usability feature.

Spread spectrum is not optional USB mandates down-spread SSC — the clock is modulated roughly 0 to −5000 ppm at a modulation rate in the low tens of kilohertz. It spreads the emissions energy across a band instead of concentrating it in a narrow spike, which is what makes the emissions scan pass. The cost lands on the receiver: the CDR must track a continuously moving clock, so SSC tracking is a real part of the jitter budget and a real part of receiver testing. Simulating a USB link with a fixed-frequency clock omits a term that the specification assumes is there.

Where the margin goes

Sign-off

USB compliance is a defined test rather than an in-house simulation flow. The transmitter is measured through a specified reference channel with a specified reference equaliser and must produce an eye that clears the compliance mask. The receiver is tested the other way round: a deliberately stressed signal — calibrated amounts of random jitter, sinusoidal jitter, ISI and SSC — is applied, and the receiver must maintain the specified error rate. Passing your own simulation is not the deliverable; passing the compliance fixture is.

Sources

Why this decides how your board behaves

What to do about it

Spend less than your allocation. Shorter routes, fewer vias, better launches than the budget strictly requires. The remaining margin helps accommodate cable variation that was not included in the original test set.

Design the connector footprint deliberately. Ground provision, antipad geometry, via stubs on through-hole pins. It is the highest-leverage part of the channel you own. See connectors and cables.

Treat shield termination as a return-path decision. A 360° bond gives common-mode current a defined low-inductance path; a pigtail does not, and the shield stops working above the frequency where its inductance dominates.

Keep the pair symmetric right up to the connector. Mode conversion on your board becomes common-mode current on someone's cable, and that is what fails an emissions scan.

Using this to find a fault
  • Works with one cable and not another. Expected, and informative: it tells you the margin is thin, not that the design is wrong. Measure with a known-good cable to separate your board from the cable.
  • Emissions failure that appears only with a cable attached. Common-mode current leaving on the cable. Look at pair symmetry and shield termination before filtering anything.
  • Compliance passes and real devices fail. The reference setup is not your setup. Compare what the compliance channel assumed against what your product has.
  • Marginal only at the far end of a long cable. Loss, which you cannot fix — so the question becomes how much of your own budget you can hand back.
Go deeper — what AC coupling and common mode really do here

USB links are AC-coupled, with series capacitors in each line of the pair. That serves a practical purpose: two devices designed independently need not agree on a common-mode voltage, and the capacitors let each end set its own.

It has two consequences worth knowing. Low-frequency content is blocked, which is why the encoding must guarantee enough transitions — a long run of identical bits would drift. And the capacitors are a discontinuity: real parts have package inductance and a footprint, and at the top of the band they are not the short circuit the schematic implies.

Common mode is the part that leaves the product. Differential current on a well-matched pair largely cancels in the far field. Common-mode current does not — it flows out along the cable, using the shield and whatever else it can find as a return, and radiates from a structure the size of the cable.

That makes the chain worth stating explicitly, because it crosses three topics that are usually treated separately: asymmetry on your board → mode conversion → common-mode current → an emissions failure caused by a cable you did not design. See differential signalling for the conversion mechanism and SCD21 as the measurement that predicts it.

On sourcing. The rates and unit intervals here are arithmetic. The revision-specific details — which test points apply, what the compliance channel is defined as, the exact encoding per generation — are recorded in the claim ledger and should be read from the USB-IF specification for the revision you are designing to.

In the real world

USB is the interface most likely to be treated as solved and most likely to produce a late surprise, because the failure usually arrives from outside: a cable, a hub, a device, or an emissions scan with something plugged in that was not there during development.

The defence is margin rather than analysis. You cannot simulate a channel you have never seen, so the engineering move is to make your third of it as good as you reasonably can and leave the rest of the budget for whatever turns up.

Related

Sources

Rows marked with a claim id are tracked in the claim ledger, which records what each source can and cannot establish.