Transmission-Line Termination Schemes

Why a resistor stops a reflection at all

If you have read the reflections page, you know that a signal bounces back and forth between two mismatched ends of a trace until the energy dies out. The natural follow-up question is: how do I make it stop? The answer is almost always a resistor — but which resistor, placed where, and at what cost, is where the real engineering lives.

The core idea is simple. A reflection exists because the load’s V/I relationship disagrees with the wave’s V/I relationship (which is Z₀). A termination resistor is a component whose V/I ratio already matches Z₀, so there is nothing left to argue about and no reflected wave is generated. Every scheme on this page is a variation on that one idea — differing only in which end gets the match, how much power the match costs, and whether the net can have more than one receiver.

A wave travelling down a line carries a fixed ratio of voltage to current, set by Z₀. When it reaches the end, whatever is there imposes its own relationship between voltage and current — Ohm's law, for a resistor. If the two disagree, the only way to satisfy both is to launch a second wave back the other way, and that second wave is the reflection.

So a terminator is not absorbing anything clever. It is simply a resistor whose V/I ratio already matches the line's, so there is nothing left to reconcile and no second wave is needed. That is the whole mechanism, and it is why the value matters so much more than the part.

Γ = ( R − Z₀ ) / ( R + Z₀ ) 0 at a match, +1 at an open, −1 at a short. A 50 Ω resistor on a 60 Ω line still reflects 9%.

Kill either end — and what each end costs

A reflection needs two mismatched ends to keep bouncing. Match the source and the echo is absorbed when it gets home; match the load and there is no echo in the first place. Both give a clean waveform, and they cost completely different things.

Scheme	Where	DC power	Swing at receiver	Typical use
Series	at the driver	none	full, after one T_d	point-to-point control nets
Parallel to GND	at the load	V_load²/Z₀ while high	V_s·R_L/(R_s+R_L)	rare on its own
Thevenin split	at the load	continuous, both states	full, biased	legacy DDR command/address
AC (R + C)	at the load	none DC; C·V²·f AC	full	clocks with a fixed duty cycle
On-die (ODT)	inside the receiver	gated per burst	full	LPDDR5X, PCIe, USB, UFS

Reading the table

Series termination is the bargain of the group: one resistor, zero DC current, and the receiver still sees the full rail. It works by matching the source instead of the load — the driver's own output impedance plus the series resistor add up to Z₀, so when the echo comes back from the unterminated far end it finds a match and is absorbed.

That mechanism has a consequence people get caught by. On the way out, the driver and the resistor form a divider with the line, so only half the swing sets off down the trace. The full amplitude only appears at the far end, where the open circuit doubles it. For one round trip, the middle of the line sits at half rail. A receiver tapped off the middle sees that half-amplitude step and may well decide it is a valid logic level. Series termination and multi-drop do not mix, and this is why.

Parallel to ground costs real current, and it is worth doing the divider rather than assuming a half. Once the line has settled, the driver and the terminator are simply a resistive divider: V_load = V_s·R_L/(R_s + R_L). You get exactly half the swing only when the source impedance equals the terminator — a 10 Ω driver into 50 Ω delivers 83% of the rail, not 50%.

The power follows from the voltage actually across the resistor, not from the rail. With an ideal low-impedance driver on a 1.2 V rail, 50 Ω draws 24 mA and dissipates about 29 mW per net, while high; with a realistic 10 Ω driver the load sees 1.0 V and the terminator burns about 20 mW, with the rest in the driver. Either way, on a 32-bit bus it is most of a watt of pure termination loss — which is why it rarely appears alone, and why the Thevenin variant — two resistors whose parallel combination equals Z₀, biased to mid-rail — draws current in both states and was abandoned for anything battery-powered.

AC termination puts a capacitor in series with the resistor so the DC path disappears. It works well on a clock, where the duty cycle is fixed; it does badly on data, because a long run of identical bits lets the capacitor charge and the termination stops terminating. Size the capacitor so RC is several times the round trip — a few tens of pF is typical — and remember you have traded DC power for switching power.

Why everything moved on-die A resistor on the board is a via and a stub away from the receiver pad. At 8533 MT/s that parasitic inductance undoes most of what the termination was supposed to buy. Putting it inside the pad removes the stub — and lets the controller enable it only during a burst, which is the only reason the power budget survives. LPDDR5X and the serial interfaces all take this route, with the value selected during training rather than fixed at layout.

How to choose

The decision is usually made for you by two questions, in this order.

Is the net point-to-point? If yes, series termination is almost always the right answer: no DC power, full swing at the receiver, one cheap part. If no — if there is more than one receiver — series is off the table and you need the termination at the far end, or at each end.

Can you afford the DC current? Parallel and Thevenin both burn power continuously, which on a wide bus is watts. If the answer is no and the net is not point-to-point, you are into AC termination or on-die termination, and on anything modern it is on-die.

Then get the value right. A terminator that is 20% off is not 80% effective — it leaves a reflection of about 10%, which is small but not nothing, and it is small in a way that compounds with everything else in your budget. Resistor tolerance, on-die termination calibration accuracy and the impedance tolerance of the trace all stack here, which is why controlled-impedance boards and calibrated ODT exist at all.

A quick decision tree. For most modern designs the path is short: (1) if the interface spec defines the termination — as DDR, PCIe, USB, and UFS all do — follow it exactly; (2) for custom or legacy nets, ask whether it is point-to-point and whether you can afford DC current, and the table above gives the answer; (3) on anything running above ~3 GT/s, assume ODT unless the spec says otherwise, because the stub inductance of a board-mounted resistor at those rates costs more signal quality than the termination buys.

Using this to find a fault

A step at half amplitude, lasting one round trip. That signature is series termination seen from the middle of a line. Either a receiver is tapped where it should not be, or you are probing the middle of a net and mistaking the normal behaviour for a fault.
Ringing that termination did not fix. Check what the termination is actually connected to before changing its value. A parallel terminator whose ground return is a long way from the signal's return path is not terminating into Z₀; it is terminating into Z₀ plus the inductance of that detour.
A net that works with ODT on and fails with it off, or vice versa. Read the ODT calibration result, not the configuration register. Training picks a value; if the calibration reference is wrong, the register says 40 Ω and the silicon is not.
Overshoot only on the first edge after an idle period. Look for AC termination with too small a capacitor, or a gated ODT that enables a beat late.

Go deeper — why series termination gives full swing, and what a stub costs

Series termination looks like it should lose half the signal, and the reason it does not is worth following once properly. Take a 1 V driver with 10 Ω output impedance, a 40 Ω series resistor and a 50 Ω line with an open far end.

At the instant of switching, the line looks like a 50 Ω resistor — the far end has not been heard from. The divider is 50/(10 + 40 + 50), so 500 mV sets off down the trace.
After one T_d it reaches the open end, where Γ = +1. The reflected wave is another 500 mV, and the far end sits at the sum: 1 V, the full rail.
After another T_d the reflection arrives back at the driver, which now presents 10 + 40 = 50 Ω — a match. Γ_s = 0, nothing is sent back out, and the whole line settles at 1 V.

So the receiver gets full amplitude, and it gets it in two steps rather than one. The cost is that extra T_d of delay before the level is valid, and the half-amplitude plateau in between — which is invisible at a single far-end receiver and fatal to anything tapped off the middle.

The other thing worth quantifying is the stub. A board-mounted terminator sits at the end of a short piece of trace and a via, and that path is not part of the matched line. Call it 2 nH of loop inductance. At the knee frequency of a 50 ps edge — 10 GHz — that is ωL ≈ 126 Ω, which is comfortably larger than the 50 Ω you were trying to match to. The terminator is still there at DC and has largely stopped working at the frequencies where reflections happen.

That calculation is the entire argument for on-die termination, and it is also the reason a board terminator's placement matters more than its tolerance. A 1% resistor 5 mm from the pad is worse than a 5% resistor at the pad.

One more subtlety on Thevenin termination. The two resistors do two jobs: their parallel combination sets the AC impedance, and their ratio sets the DC bias point. Those are independent, which is useful — you can bias a net to 0.7 V for a receiver that wants it while still presenting 50 Ω — and it is also a trap, because getting the parallel combination right while getting the ratio wrong gives you a perfectly terminated net sitting at the wrong common-mode voltage.

In the real world

The most common termination failure is not a wrong value. It is a terminator that is present, correct and connected to the wrong reference — a parallel terminator pulled to a ground that is not the plane the signal is referenced to, or an AC terminator whose capacitor returns through a via to a different plane. In both cases the schematic is right and the net rings anyway, because the termination's return current has to travel a loop that the line does not have.

The habit worth building: when you place a terminator, look at where its return goes, not just what it connects to. A terminator is part of the transmission line, and a transmission line is a signal path and a return path.

Transmission-Line Reflections and Ringing — what you are fixing
When does a trace become a transmission line? — whether you need to fix it
Return-Current Paths and Reference Continuity — why a terminator's ground matters
Transmission-Line Characteristic Impedance — the number you are matching to
Lab A — travelling waves — step through each scheme and watch the energy account