Signal Bandwidth: Why Edge Rate Matters

Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.

Start with what a digital signal really looks like

Picture a 10 MHz reset line on a board. The clock rate is low, the net is short, and nothing in the schematic review suggests it needs attention. Then the prototype arrives and an oscilloscope shows 800 mV of ringing on every edge — enough to false-trigger the downstream logic. The clock frequency is only 10 MHz, but the output buffer driving that reset has a 200 ps rise time. That edge carries energy up past 2.5 GHz, and the trace is responding to that, not to the 10 MHz repetition rate.

This scenario is the single most common surprise in board bring-up, and it comes from a natural but wrong assumption: that a slow clock means a slow signal. The rest of this page explains why edge rate — not clock rate — decides which frequencies your interconnect must handle.

On a timing diagram a logic signal is drawn as a rectangle: it is low, then it is high, and the change between them is a vertical line. Real electronics cannot do that. Charging the capacitance of a trace and the input it drives takes time, so every real transition is a ramp. The time that ramp takes is the rise time, usually written t_r, and by convention it is measured between the 10% and 90% points rather than end to end.

Rise time connects the waveform to the frequency range that the interconnect, package, probe, and receiver must preserve. Fourier analysis makes that connection explicit.

Any signal is a sum of sine waves

Fourier's result is that any repeating waveform can be built by adding together sine waves at multiples of its repetition rate. Those multiples are called harmonics. A 100 MHz square wave is a 100 MHz sine, plus a smaller 300 MHz sine, plus a smaller-still 500 MHz sine, and so on upward forever.

Forever, that is, if the wave is perfectly square. The corners are what need the very high harmonics — a sharp corner is exactly the thing a slow sine wave cannot make. So when you round the corners by giving the edge a finite rise time, the high harmonics stop being needed and their amplitudes collapse. How square the corner is decides how high the frequency content goes.

Turn that around and you have the whole page. The repetition rate sets the lowest frequency in the signal and the spacing of the harmonics. The rise time sets the highest one worth worrying about. They are two independent knobs. Many signal-integrity surprises begin when a review uses repetition rate to set the analysis bandwidth even though the interconnect is responding to the edge spectrum.

f_knee ≈ 0.5 / t_r The knee is where the harmonics start falling off much faster. A 300 ps edge puts the knee at 1.7 GHz — whether that edge happens once a second or a billion times a second.

Drag the rise-time slider on the panel above and watch the envelope. Below the knee the harmonics fall off gently, at 20 dB per decade. Above it they fall off at 40 dB per decade — twice as steeply — which makes the knee a useful starting point for setting an analysis band. It is not a cutoff: content continues above it, and a sharp resonance there can still matter. Extend the model far enough to show that omitted content and out-of-band discontinuities no longer change the result you care about.

Why this decides how your board behaves

Interconnect loss, reflection, and coupling are frequency-dependent, while data rate sets the timing and pattern context in which those effects accumulate. Keeping those roles separate makes the consequences easier to predict:

Reflections. A trace rings when the round trip down it and back is long compared with the edge. It is the edge in that comparison — so slowing the edge is a real fix, and slowing the clock is not. Critical length is built entirely out of t_r.
Crosstalk. A neighbouring trace picks up a voltage proportional to how fast yours is changing, not to how often. Halving the rise time doubles the crosstalk, at any clock rate at all. See crosstalk.
Loss. Copper and dielectric both attenuate more at high frequencies. A faster edge puts more energy up where the loss is worst, so it is the part of your signal that gets damaged first — which is why a long trace makes edges slower, and slower edges make timing worse. See loss mechanisms.
Emissions. Radiated energy climbs steeply with frequency. Boards that fail EMC may be improved by slowing an edge that is faster than the timing requirement needs.

What the clock rate still decides This is not a claim that the data rate is irrelevant — it decides how much room you have to survive all of the above. The unit interval comes straight from the rate, and every timing budget is measured in UI. The rate also decides how many bit periods the channel's memory stretches across, which is what turns loss into ISI.

Put simply: the edge decides what frequencies exist; the rate decides how much time you have to recover from them. A 10 MHz bus with a 300 ps edge has a genuine 1.7 GHz problem — and a 100 ns bit period to absorb it, which is exactly why it usually gets away with it and occasionally does not.

What to do about it

Three things, in the order you should reach for them.

First, establish the edge and its conditions. A datasheet value may be a limit, a typical measurement, or a value at one load and voltage. For reflection and coupling analysis, inspect the fastest relevant voltage-temperature-process corner and package/load condition in the available I/O model. Record whether the value is 10–90% or 20–80% before using it in a bandwidth or electrical-length calculation.

Second, slow the edge deliberately where the timing budget permits. A series resistor at the driver, or a supported slew-rate control setting, can reduce reflections, crosstalk, and emissions together because it reduces the high-frequency content that all three feed on. The constraint is timing: a slower edge eats setup margin and adds jitter on a slow-moving crossing. On a control net with nanoseconds to spare, it is often an efficient option after checking the receiver thresholds and timing corners.

Third, check which convention you are being given. Rise time is quoted two ways. 10–90% is the signal-integrity convention; 20–80% is common in serial-link specifications because it is easier to measure cleanly once loss has rounded the ends of the edge. For a roughly Gaussian edge the 20–80% figure is about 0.6× the 10–90% one, so mixing them makes an edge look almost twice as slow as it is — and every critical-length and knee calculation built on it comes out wrong in the dangerous direction.

Using this to find a fault When a slow bus misbehaves, the instinct is to look at the clock. Look at the edge instead.

Ringing on a slow control net. Measure t_r, not the period. Compare it with twice the trace delay. If 2·T_d is more than about a third of t_r, treat the net as a transmission line and evaluate its termination.
Crosstalk that appears only on some nets. Look for which driver library they share. A single fast buffer type reused for chip selects will light up every victim around it.
An EMC failure at a frequency with no obvious source. Divide 0.5 by your fastest edge. If the failing frequency is below that number, the edge is a candidate. Where timing allows, source damping may be more efficient than containing radiation after it is created.

Go deeper — where the two corner frequencies come from, and the third number

The panel draws the exact envelope, and the two corner frequencies are a summary of it rather than a replacement. The waveform is a trapezoid: a pulse of width τ with edges of duration t_r. Its spectrum is the product of two sinc functions, one from the pulse width and one from the ramp, and each sinc contributes a corner.

|A_n| ∝ |sinc(nπτ/T)| · |sinc(nπt_r/T)| the first corner at 1/(πτ) takes the envelope from flat to −20 dB/decade; the second at 1/(πt_r) takes it to −40

So the −40 dB/decade region really begins near 1/(πt_r) ≈ 0.32/t_r, and 0.5/t_r is a deliberately conservative round-up of it. That is the honest status of the knee: a rule of thumb chosen to err on the safe side, not a derived constant.

Three numbers get quoted interchangeably here and they answer different questions. None of them is a spectral cutoff — the spectrum above has no cutoff anywhere, it just falls off faster past the second corner.

0.35 / t_r is the −3 dB bandwidth of a single-pole low-pass filter that would produce that rise time. It answers “what analogue bandwidth do I need so this edge comes through without being noticeably slowed?” It is the right number for sizing a probe, an amplifier or a scope.
0.5 / t_r is the knee. It answers “above what frequency does the channel stop mattering much?” It is the right number for deciding how far up you need a model to be accurate.
The ramp envelope is the exact answer and it is a curve, not a number. When the two disagree by enough to matter, believe the curve.

A useful sanity check on all of this: a 50% duty-cycle square wave has no even harmonics at all, because the first sinc goes to zero exactly there. Set the duty to 50% on the panel and the 2nd, 4th and 6th harmonics disappear. Nudge it off 50% and they come back. That is a closed-form result the model has no special case for, so it is a good way to convince yourself the spectrum on screen is real.

One more consequence worth internalising. Because loss rises with frequency and the edge is where the high frequencies live, a channel slows its own edges down as the signal travels. The edge that arrives is not the edge that left. So “the rise time” is not one number for a net — it is fast at the driver, where reflections and crosstalk are generated, and slow at the receiver, where timing is judged. Both matter, and they are not the same problem.

In the real world

The classic version of this failure is a memory interface that passes every simulation and then shows marginal failures on hardware, traced to a chip-select or reset line routed as an afterthought because “it is only switching at a few megahertz”. It is unterminated, it is long, it runs beside something that matters, and it is driven by the same fast buffer as everything else on the die. The clock rate said it was harmless. The edge rate said otherwise.

Ask both “how fast is this edge?” and “how long is this trace compared with the edge?” alongside the bus rate. Together they determine whether distributed behavior must be included; the data rate then sets the available timing margin and pattern memory.

When does a trace become a transmission line? — the rule built directly on t_r
PCB Transmission-Line Loss Mechanisms — why the edge arrives slower than it left
Transmission-Line Reflections and Ringing — what a fast edge does to an unterminated net
PCB Crosstalk: NEXT, FEXT, and Mutual Coupling — coupling scales with dV/dt
Lab D: ADC Interference, Aliasing and Reference Noise — the same edge rate decides how much of a switching line reaches a converter, and how far up the spectrum it goes