Interface sign-off / 07
UFS 3.1 vs 4.0 vs 5.0: M-PHY Gears, Burst Mode and Signal Integrity
UFS is the storage link inside a phone: MIPI M-PHY lanes, two in each direction, running a short distance from the processor to the flash. UFS 4.0 and 4.1 run HS-G5 at 23.32 Gb/s per lane; UFS 5.0 doubles that to 46.6 Gb/s with PAM4 HS-G6, at almost the same Nyquist frequency of about 11.7 GHz. Because the channel is short, most of the signal integrity work is less about loss than about the edges of each transfer: the receiver re-locks at the start of every burst, the PHY wakes from deep sleep on its own schedule, and the supply rail sees every one of those transitions.
At a glance
UFS 3.1 vs 4.0 vs 5.0: what is the difference?
Each step doubled the rate on each lane. UFS 3.0 (2018) and 3.1 (2020) use M-PHY HS-G4 at up to 11.6 Gb/s per lane; UFS 4.0 (2022) moved to M-PHY v5.0 and HS-G5 at 23.32 Gb/s; UFS 5.0 (2026) moves to M-PHY v6.0 and HS-G6, which uses PAM4 to carry 46.6 Gb/s (C-157, C-158, C-12c, C-161). All of them use two lanes in each direction. The versions table lines them up.
How fast is UFS 4.0?
Two HS-G5 lanes carry 46.64 Gb/s on the wire in each direction. After 8b10b coding that is 4.66 GB/s, and JEDEC quotes about 4.2 GB/s for reads and writes, roughly 90% of it once the protocol takes its share (C-159, C-163). UFS 3.0 and 3.1 reach 23.2 Gb/s on the wire over two HS-G4 lanes (C-157).
Is UFS 4.1 faster than UFS 4.0?
No. UFS 4.1 keeps M-PHY v5.0, UniPro v2.0 and about 4.2 GB/s, and is hardware compatible with UFS 4.0; its changes are in device and host-controller features such as defragmentation and WriteBooster management (C-160). For signal integrity, a UFS 4.1 link is a UFS 4.0 link.
What changes in UFS 5.0 for signal and power integrity?
Four things. The top gear becomes HS-G6, which uses four-level PAM4 signalling at up to 46.694 Gb/s per lane; a new 1b1b line coding cuts the coding overhead below 10%; the link gains equalisation and training; and UFS 5.0 gives the PHY its own supply rail, isolated from the memory subsystem’s noise (C-161, C-162). JEDEC quotes up to about 10.8 GB/s over two lanes.
Does UFS power down between bursts?
Not completely, and the difference matters. Between high-speed bursts an M-PHY lane waits in STALL, which it leaves in nanoseconds; every new burst opens with a synchronisation sequence on which the receiver re-locks. Only a longer idle sends the lane to HIBERN8, an ultra-low-power state whose exit takes hundreds to thousands of microseconds (C-163). The burst section shows both.
How long can a UFS trace be?
The channel limits are in the M-PHY specification, which only MIPI members can read, and the UFS standard itself is sold by JEDEC, so this page does not quote a length or a loss budget. The SoC and flash vendors’ layout guidelines are where a board designer gets those numbers.
Is UFS 5.0 backward compatible?
JEDEC describes UFS 5.0 as compatible with UFS 4.x hardware, UFS 4.1 as hardware compatible with UFS 4.0, and UFS 4.0 as backward compatible with UFS 3.1 and 3.0 (C-159, C-160, C-161). M-PHY v5.0 itself is backward compatible through v4.1 (C-162).
Why UFS is a short link with a power problem
Most of the signal integrity concerns on this site grow with distance. UFS runs a short way from the processor to the flash inside a phone, so the reach questions that dominate PCIe or USB barely arise. What dominates instead is power. A phone cannot afford a link that draws full current while it waits, so M-PHY idles between transfers and wakes for each one.
That one design choice is where the engineering is. A link that is always on settles once; a link that idles and wakes has to settle correctly every time. Settling involves references, bias currents, clock recovery and, from UFS 5.0, equaliser training, and none of those are instantaneous. The signal integrity question shifts from “is the eye open?” to “is the eye open early enough in each burst, with whatever else woke up at the same moment pulling on the supply?”
UFS 3.0, 3.1, 4.0, 4.1 and 5.0, side by side
| UFS 3.0 | UFS 3.1 | UFS 4.0 | UFS 4.1 | UFS 5.0 | |
|---|---|---|---|---|---|
| JEDEC standard, published | JESD220D, Jan 2018 | JESD220E, Jan 2020 | JESD220F, Aug 2022 | JESD220G, Dec 2024 | JESD220H, Feb 2026 |
| M-PHY, UniPro | v4.1, v1.8 | v4.1, v1.8 | v5.0, v2.0 | v5.0, v2.0 | v6.0, v3.0 |
| Top gear | HS-G4, NRZ | HS-G5, NRZ | HS-G6, PAM4 | ||
| Rate per lane, on the wire | up to 11.6 Gb/s | 23.32 Gb/s | 46.6 Gb/s | ||
| Lanes | two in each direction | ||||
| Unit interval | 86 ps | 42.9 ps | 42.8 ps per symbol | ||
| Nyquist frequency | 5.8 GHz | 11.66 GHz | 11.67 GHz | ||
| Line coding | 8b10b (C-163) | 1b1b, overhead below 10% (C-162) | |||
| JEDEC’s quoted throughput | 23.2 Gb/s on the wire | about 4.2 GB/s | about 10.8 GB/s | ||
| Added for the link | Adapt: channel monitoring and training | DeepSleep state | High Speed Link Startup, Eye Monitor | no PHY change | link equalisation, separate PHY supply rail |
| Sources | C-157 | C-158 | C-12c, C-159 | C-160 | C-12d, C-161, C-162 |
Two rows deserve a second look. The unit interval halves from UFS 3.1 to 4.0 and then stays put, because HS-G6 sends two bits in each symbol. And the “added for the link” row is a short history of how a burst link gets harder: UFS 3.0 added receiver adaptation, UFS 4.0 a way to see the eye inside the receiver, and UFS 5.0 full link equalisation and a quieter supply.
M-PHY burst mode: STALL, HIBERN8 and the SYNC sequence
M-PHY carries data in high-speed bursts. Each burst opens with a PREPARE period and then a synchronisation sequence, SYNC, on which the receiver’s CDR locks to the incoming phase and frequency; the length of that sequence is chosen by the application rather than fixed by the PHY specification (C-14, C-163). Between bursts the lane waits in STALL, and the return to a burst takes nanoseconds. For longer idles the lane can go to HIBERN8, an ultra-low-power state that keeps its configuration but takes hundreds to thousands of microseconds to leave (C-163). M-PHY also has a slow pulse-width-modulated mode, whose clock is embedded in each bit’s pulse width, so it needs no CDR at all (C-163).
So the receiver’s job is not to lock from nothing on every burst. It is to lock quickly and reliably on a short SYNC after a STALL, and to come back cleanly from HIBERN8 when the system asks. The two have different failure modes: a SYNC too short for the real receiver after a STALL loses the first data of a burst, while a slow or noisy wake from HIBERN8 shows up as an occasional failed link startup.
Sleeping is not free either. HIBERN8 saves the difference between STALL’s power and its own for as long as the lane sleeps, and pays for the wake: the energy drawn while the PHY comes back, and the time the next transfer waits for it. Sleeping pays once the time asleep is longer than the wake’s energy divided by that saving. If waking draws about what STALL does and HIBERN8 draws next to nothing, that break-even is about the wake time itself. A lane that waits a threshold before it sleeps spends the threshold in STALL either way, so its break-even idle is the threshold plus that. The panel’s state powers are illustrative, since M-PHY’s own are in the members-only specification; the shape of the trade does not depend on them. Before you try it, set the threshold below the gaps the traffic really has, then guess what happens as you shrink the gaps below the break-even.
Best viewed on a laptop or desktop. These panels are built so you can move a slider and watch several charts answer at once. A phone has no room to put them side by side.
HS-G5 vs HS-G6: PAM4 doubles the data, not the Nyquist frequency
The NRZ vs PAM4 page works through the 9.5 dB in detail. For a UFS board it means the HS-G5 rule of thumb, that a short channel has loss to spare, holds less well at HS-G6: the loss at Nyquist is about the same, but the eye that loss has to leave behind is a third the size, so crosstalk, reflections and supply noise each take a bigger share of what is left.
Where the margin goes
- The escape, not the trace. Getting four differential pairs out of a fine-pitch processor ball field, through the layer transitions a thin phone stackup allows, without breaking pair symmetry, is where the discontinuities are.
- Crosstalk from everything else on the board. A handset routes this link alongside LPDDR, camera and display interfaces, RF and the power distribution network, with little room to separate them. The aggressors are unrelated to the data, so their coupling appears as bounded, uncorrelated jitter.
- Supply noise at the wake. The moments a burst starts or the PHY leaves HIBERN8 are the moments its current changes fastest. UFS 3.1 added a low-power state for systems that share regulators with other functions (C-158), and UFS 5.0 gives the PHY a separate rail for noise isolation (C-161): the standard itself treats the supply as part of the link.
- Mode conversion from asymmetric escape routing, which the receiver does not reject and which couples into neighbouring nets.
- Spread spectrum, where the PHY configuration uses it. Do not assume USB’s parameters carry across to M-PHY without checking the revision you are designing to (C-13).
How UFS links are signed off
M-PHY conformance is defined by MIPI’s conformance test suite, which is members-only, but the test equipment vendors describe its shape (C-164). The transmitter is measured at its own pins, with the HS-G4 and HS-G5 eyes accumulated to a bit error ratio of 10−6 and extrapolated to 10−12. The receiver is fed a calibrated stressed signal, including a conformant channel that adds intersymbol interference, and must report zero errors: at least 3×1010 bits for a 10−10 target, or 3×1012 for 10−12.
A burst-mode link needs more than that. The useful additions are checks with no equivalent on a continuous link: acquisition within the SYNC sequence the system actually configures, and clean behaviour through STALL and HIBERN8 transitions at the temperature and voltage corners where the PHY is slowest to wake. From UFS 4.0, M-PHY’s Eye Monitor shows the health of the received eye for debug (C-159, C-162), which can turn some of that from a lab measurement into something checked in the product itself.
Why this decides how your board behaves
- Transient behaviour matters more than steady state. The first bits after a STALL or a wake are the ones at risk, and a steady-state eye measurement never shows them.
- The supply sees a repeating load step. Bursting and sleeping is a current transient at a rate the system’s traffic sets, and if that rate lands near a resonance of the power distribution network, it is excited repeatedly rather than once. See anti-resonance.
- Loss is rarely the first constraint. On a short channel, crosstalk, return paths and supply noise usually take the margin first, and at HS-G6 each of them takes a bigger share.
What to do about it
Test at the burst boundaries, not in the middle. A long steady capture measures the easy case. The interesting question is what the first symbols after a STALL or a wake look like.
Check the supply at the traffic’s burst rate. The load’s spectrum follows the storage traffic, so compare the rates your workloads produce against the power network’s impedance curve, and keep the PHY’s supply as quiet as the standard now asks for.
Give each pair a clean, continuous reference through the routing. In a phone the routing is dense, flexible-circuit transitions are common, and the return path is where the surprises are.
Keep each pair symmetric through every transition. Short channel or not, mode conversion still converts, and a handset has plenty of asymmetric structures to convert at.
- Errors clustered at the start of a burst. Settling: references, bias, CDR lock on SYNC, or equaliser adaptation. Steady-state measurements will look clean.
- An occasional failed link startup. Look at the wake from HIBERN8 and the supply during it, not at the data eye.
- Failures that depend on the traffic pattern rather than the data. Compare the burst rate against the power network’s impedance curve.
- A link that works on a rigid board and fails through a flex. Impedance and return path through the flex and its connectors, which are rarely modelled.
- Marginal on one board build only. If the PHY offers it, read the Eye Monitor across builds before reaching for a scope.
Go deeper — the throughput arithmetic, what a wake has to do, and what is not sourced here
From line rate to GB/s. Two HS-G5 lanes carry 2 × 23.32 = 46.64 Gb/s. 8b10b coding sends ten bits for every eight of data, leaving 37.3 Gb/s, which is 4.66 GB/s. JEDEC’s “about 4.2 GB/s” for UFS 4.0 is about 90% of that, the rest going to the link and transport protocol (C-159, C-163). UFS 5.0’s 1b1b coding has overhead below 10% (C-162): two lanes at 46.6 Gb/s carry 11.65 GB/s before protocol, and JEDEC’s about 10.8 GB/s is about 93% of it (C-161). Most of UFS 5.0’s doubling comes from the gear; the coding change adds the rest.
What a wake has to do. Leaving a deep low-power state is not one event. Bias currents and references settle, which is analogue and sets a floor on how fast a wake can be; the clock recovery loop acquires lock, which needs enough transitions to pull in; any adaptive equalisation converges or restores stored settings; and where the line idled unterminated, the termination and the common-mode level have to settle. Those steps are why a burst link’s specification has wake timings at all, and why deeper sleep and faster wake trade against each other: the more completely the PHY powers down, the more of that list it redoes.
A diagnostic asymmetry. A steady-state eye on a burst link measures the part of operation that was never in doubt. The errors, if there are any, sit at the boundaries that the eye’s own averaging discards.
What is not sourced here. M-PHY’s electrical limits, its channel model and its equalisation settings are in specifications only MIPI members can read, and JEDEC sells the UFS standards. This page therefore quotes rates, versions and features from the standards bodies’ public releases, the burst and state structure from an M-PHY v1-era article, and the conformance framework from test-equipment vendors, each recorded in the claim ledger with what it can and cannot establish. The engineering reasoning does not depend on the missing numbers; a sign-off does.
In the real world
UFS is a useful reminder that a fast link and a hard link are not the same thing. The channel is short and forgiving; the difficulty lives in power management, in a mechanical environment full of flexes and connectors, and in a system that spends most of its time asleep.
So instincts built on long-channel links can mislead here. The useful question is rarely how much loss there is. It is usually what happens in the first moments after something wakes up, and from UFS 5.0 onwards, how much of a smaller PAM4 eye is left once the neighbours and the supply have taken their share.
Related
Sources
- MIPI Alliance — M-PHY v5.0 announcement C-12a
- JEDEC — JESD220F UFS 4.0 announcement C-12c
- JEDEC — UFS 5.0 announcement C-12d
- Mixel — M-PHY benefits and challenges C-14
- JEDEC — UFS 3.0 (JESD220D) announcement C-157
- JEDEC — UFS 3.1 (JESD220E) announcement C-158
- JEDEC — UFS 4.1 (JESD220G) announcement C-160
- MIPI Alliance — M-PHY specification page C-162
- Granite River Labs — MIPI M-PHY receiver conformance testing C-164
Rows marked with a claim id are tracked in the claim ledger, which records what each source can and cannot establish.