{
  "schemaVersion": 1,
  "id": "pdn-shared-dc",
  "kind": "pdn-dc",
  "model": "labPdn",
  "modelVersion": "1.3",
  "contractVersion": "2.3",
  "params": {
    "rvrm": 4,
    "fbw": 120,
    "lplane": 900,
    "lpkg": 350,
    "cboard": 1,
    "nboard": 20,
    "esr": 20,
    "esl": 1100,
    "cdie": 200,
    "imax": 8,
    "tr": 800,
    "zt": 10,
    "imax2": 3,
    "tr2": 800,
    "startNs": 786.4,
    "widthNs": 1835,
    "start2Ns": 786.4,
    "width2Ns": 1835
  },
  "topology": "The existing five-stage VRM/bulk/board/package/die ladder, one board and one die load.",
  "planes": "Observe board and die relative to the ideal regulator reference; withdrawals are positive and rail deviation is negative.",
  "evidence": {
    "type": "analytical",
    "provenance": "First-principles boundary conditions, linear circuit laws or the declared teaching-loop equation; no measured or licensed data."
  },
  "checks": [
    {
      "metric": "zDieDie",
      "expected": 0.0078,
      "absoluteTolerance": 1e-10,
      "unit": "ohm",
      "derivation": "DC capacitors open, inductors short: .004+.0004+.0006+.0008+.002 Ω."
    },
    {
      "metric": "zBoardBoard",
      "expected": 0.005,
      "absoluteTolerance": 1e-10,
      "unit": "ohm",
      "derivation": "Shared source-to-board DC path: .004+.0004+.0006 Ω."
    },
    {
      "metric": "zDieBoard",
      "expected": 0.005,
      "absoluteTolerance": 1e-10,
      "unit": "ohm",
      "derivation": "A board injection creates voltage across the shared source-to-board resistance; downstream DC current is zero."
    },
    {
      "metric": "zBoardDie",
      "expected": 0.005,
      "absoluteTolerance": 1e-10,
      "unit": "ohm",
      "derivation": "A die injection flows through the same source-to-board resistance."
    },
    {
      "metric": "dieDeviation",
      "expected": -0.0774,
      "absoluteTolerance": 1e-10,
      "unit": "V",
      "derivation": "−(8 A × .0078 Ω + 3 A × .005 Ω)."
    },
    {
      "metric": "boardDeviation",
      "expected": -0.055,
      "absoluteTolerance": 1e-10,
      "unit": "V",
      "derivation": "−((8 A + 3 A) × .005 Ω)."
    }
  ],
  "lesson": {
    "prediction": "Why do the board and die have different DC voltage drops on the same rail?",
    "experiment": "Open the scenario, keep its network and stimulus fixed, and inspect the stated observation. Compare with the derived answer before changing one variable.",
    "explanation": "Only the source-to-board resistances are shared by both currents. Die current also crosses package and die series resistances. Capacitor banks do not conduct steady DC in this small-signal circuit.",
    "transferQuestion": "Can adding ideal capacitors remove this steady DC drop?",
    "answer": "No. Capacitors are open at DC; resistance or operating current must change. Capacitors can still improve finite-time excursions."
  },
  "limitations": [
    "The runner evaluates exactly 0 Hz and constant currents.",
    "The linked lab shows finite pulses and starts its frequency sweep above DC. Its droop peaks are not these DC values.",
    "VRM is a teaching approximation; no regulator-control-loop or thermal model."
  ],
  "scenario": "/topics/labs/pdn-chain.html#lab=labPdn;v=2.3;pd-fbw=120;pd-lplane=900;pd-lpkg=350;pd-nboard=20;pd-esr=20;pd-esl=1100;pd-cdie=200;pd-imax=8;pd-tr=800;pd-zt=10;pd-imax2=3;pd-tr2=800;pd-startNs=786.4;pd-widthNs=1835;pd-start2Ns=786.4;pd-width2Ns=1835",
  "parameterUnits": {
    "rvrm": "mohm",
    "fbw": "kHz",
    "lplane": "pH",
    "lpkg": "pH",
    "cboard": "uF",
    "nboard": "count",
    "esr": "mohm",
    "esl": "pH",
    "cdie": "nF",
    "imax": "A",
    "tr": "ps",
    "zt": "mohm",
    "imax2": "A",
    "tr2": "ps",
    "startNs": "ns",
    "widthNs": "ns",
    "start2Ns": "ns",
    "width2Ns": "ns"
  },
  "stimulus": "Constant 8 A die and 3 A board withdrawals for the DC reference. Scenario opens the separate finite-pulse comparison."
}